FemtoClock Crystal-to-3.3V LVPECL 8430252-45 Frequency Synthesizer DATASHEET GENERAL DESCRIPTION FEATURES The 8430252-45 is a 2 output LVPECL and LVCMOS/LVTTL One differential 3.3V LVPECL output and Synthesizer optimized to generate Ethernet reference clock One LVCMOS/LVTTL output frequencies . Using a 25MHz, 18pF parallel resonant crystal, the Crystal oscillator interface designed for a 25MHz, following fre-quencies can be generated: 156.25MHz LVPECL 18pF parallel resonant crystal output and, 125MHz LVCMOS output. The 8430252-45 uses IDTs rd 3 generation low phase noise VCO technology and can achieve A 25MHz crystal generates both an output frequency of 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter 156.25MHz (LVPECL) and 125MHz (LVCMOS) requirements. The 8430252-45 is packaged in a small 16-pin VCO frequency: 625MHz TSSOP package. RMS phase jitter 156.25MHz (1.875MHz - 20MHz) using a 25MHz crystal: 0.39ps (typical) Full 3.3V supply mode 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package PIN ASSIGNMENT BLOCK DIAGRAM Pullup OE 1 16 CLK EN OE VEE 2 15 VEE QA 3 14 QB 25MHz 5 QA XTAL IN VCCO A 4 13 nQB Phase VCO nc 5 12 VCCO B OSC 625MHz Detector QB nc 6 11 XTAL IN XTAL OUT 4 VCCA 7 10 XTAL OUT nQB VCC 8 9 VEE Feedback Divider 25 Pullup 8430252-45 CLK EN 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View 8430252-45 REVISION A 5/27/15 1 2015 Integrated Device Technology, Inc. 8430252-45 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description Output enable pin. LVCMOS/LVTTL interface levels. 1 OE Input Pullup See Table 3A Function Table. 2, 9, 15 V Power Negative supply pin. EE 3 QA Output LVCMOS/LVTTL clock output. 4V Power Output supply pin for QA output. CCO A 5, 6 nc Unused No connect. 7V Power Analog supply pin. CCA 8V Power Core supply pin. CC XTAL OUT, 10, 11 Input Crystal oscillator interface. XTAL IN is the input, XTAL OUT is the output. XTAL IN 12 V Power Output supply pin for QB, nQB outputs. CCO B 13, 14 nQB, QB Output Differential clock outputs. LVPECL interface levels. Clock enable pin. LVCMOS/LVTTL interface levels. 16 CLK EN Input Pullup See Table 3B Function Table. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN C Power Dissipation Capacitance V , V , V V = 3.465V 18 pF PD CC CCA CCO A, CCO B R Input Pullup Resistor 51 k PULLUP R Output Impedance QA V = 3.3V 20 OUT CCO A TABLE 3A. OE SELECT FUNCTION TABLE Input Output OE QA 0 Hi-Z 1 Active TABLE 3B. CLK EN SELECT FUNCTION TABLE Input Outputs CLK EN QB nQB 0 Low High 1 Active Active REVISION A 5/27/154 2 FemtoClock Crystal-to- 3.3V LVPECL Frequency Synthesizer