FemtoClock Multi-Rate 3.3V, 2.5V
843034
LVPECL Frequency Synthesizer DATA SHEET
General Description Features
The 843034 is a general purpose, low phase noise Dual differential 3.3V LVPECL outputs which can be set
LVPECL synthesizer which can generate frequencies for a independently for either 3.3V or 2.5V
wide variety of applications. The 843034 has a 4:1 input
4:1 Input Mux:
Multiplexer from which the following inputs can be
One differential input
selected: one differential input, one single-ended input, or
One single-ended input
two crystal oscillators, thus making the device ideal for
Two crystal oscillator interfaces
frequency translation or frequency generation. Each
CLK, nCLK pair can accept the following differential input levels:
differential LVPECL output pair has an output divider
LVPECL, LVDS, LVHSTL, HCSL
which can be independently set so that two different
frequencies can be generated. Additionally, each LVPECL
TEST_CLK accepts LVCMOS or LVTTL input levels
output pair has a dedicated power supply pin so the
Output frequency range: 35MHz to 625MHz
outputs can run at 3.3V or 2.5V. The 843034 also supplies
a buffered copy of the test clock or crystal frequency on
Crystal input frequency range: 12MHz to 40MHz
the single-ended REF_OUT output pin which can be
VCO range: 560MHz to 750MHz
enabled or disabled, (disabled by default). The output
frequency can be programmed using either a serial or
Parallel or serial interface for programming feedback divider and
parallel programming interface.
output dividers
RMS phase jitter at 333.3MHz, using a 22.222MHz crystal (12kHz
The phase jitter of the 843034 is less than 1ps RMS, making it
to 20MHz): 0.91ps (typical)
suitable for use in Fiber Channel, SONET, and Ethernet applications.
Supply voltage modes:
LVPECL outputs
Core/ Output
3.3V/ 3.3V
3.3V/ 2.5V
Pin Assignment REF_OUT output
Core/ Output
3.3V/ 3.3V
0C to 70C ambient operating temperature
Industrial temperature available upon request with ePad option
48 47 46 45 44 43 42 41 40 39 38 37
M8 XTAL_OUT1
1 36
Lead-free (RoHS 6) packaging
NB0 2 35 XTAL_IN1
NB1
3 34 XTAL_OUT0
ICS843034
NB2 4
33 XTAL_IN0
48-PIN LQFP
OE_REF 5 32 TEST_CLK
7mm x 7mm x 1.4mm
SEL1
OE_A 6 31
package body
OE_B
7 30 SEL0
Y Package
VCC 8 29 VCCA
Top View
NA0 9 28 S_LOAD
NA1 10 S_DATA
27
NA2 11 26 S_CLOCK
VEE MR
12 25
13 14 15 16 17 18 19 20 21 22 23 24
Integrated Device Technology, Inc 1 December 2, 2015
TEST
M7
VCC
M6
FOUTA0
M5
nFOUTA0 M4
VCCO_A M3
FOUTB0 M2
nFOUTB0 M1
VCCO_B M0
REF_OUT VCO_SEL
VCCO_REF nP_LOAD
nc nCLK
VEE CLK843034 DATA SHEET
Block Diagram
Pullup
OE_A
000 1
Pullup
001 2
VCO_SEL
010 3
011 4
XTAL_IN0
FOUTA0
100 5
OSC 00
XTAL_OUT0
101 6 nFOUTA0
110 8
XTAL_IN1
0
OSC 01 111 16
V
CCO_A
XTAL_OUT1
Phase
000 1
1
VCO
Pulldown
CLK
Detector 001 2
V
CCO_B
10
Pullup/Pulldown
nCLK 010 3
FOUTB0
011 4
Pulldown
nFOUTB0
TEST_CLK 100 5
11
M
101 6
Pulldown
SEL1 110 8
Pulldown
111 16
SEL0
Pullup
OE_B
V
CCO_REF
Pulldown
MR
REF_OUT
Pulldown
OE_REF
Pulldown
S_LOAD
Pulldown
TEST
S_DATA
Configuration
Pulldown
S_CLOCK
Interface
Pulldown
nP_LOAD
Logic
M0:M4 M6:M8 Pulldown, M5 Pullup
M8:M0
Pulldown, Pullup, Pullup
NA2, NA0, NA1
Pulldown, Pullup, Pullup
NB2, NB0, NB1
Integrated Device Technology, Inc 2 December 2, 2015