XTAL IN VEE nP LOAD nFOUT0 VCO SEL FOUT0 M0 VCCO M1 nFOUT1 M2 FOUT1 M3 VCC M4 TEST 500MHz, Crystal-to-3.3V, 2.5V Differential 8430I-61 LVPECL Frequeny Synthesizer DATA SHEET GENERAL DESCRIPTION FEATURES The 8430I-61 is a general purpose, dual output Dual differential 3.3V or 2.5V LVPECL outputs Crystal-to-3.3V, 2.5V Differential LVPECL High Frequency Selectable crystal oscillator interface Synthesizer . The 8430I-61 has a selectable TEST CLK or LVCMOS/LVTTL TEST CLK or crystal inputs. The VCO operates at a frequency range of 250MHz to 500MHz. The VCO frequency is programmed Output frequency range: 20.83MHz to 500MHz in steps equal to the value of the input reference or Crystal input frequency range: 14MHz to 27MHz crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the VCO range: 250MHz to 500MHz con guration logic. Frequency steps as small as 1MHz can be Parallel or serial interface for programming counter achieved using a 16MHz crystal or TEST CLK. and output dividers RMS period jitter: 6ps (maximum) Cycle-to-cycle jitter: 30ps (maximum) Supply voltage modes: V /V /V CC CCA CCO 3.3/3.3/3.3 3.3/3.3/2.5 -40C to 85C ambient operating temperature Available in lead-free RoHS compliant package BLOCK DIAGRAM PIN ASSIGNMENT 32 31 30 29 28 27 26 25 M5 1 24 XTAL OUT M6 2 23 TEST CLK M7 3 22 XTAL SEL M8 4 21 VCCA ICS8430I-61 N0 5 20 S LOAD N1 6 19 S DATA N2 7 18 S CLOCK MR 8 17 VEE 9 10 11 12 13 14 15 16 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 8430I-61 REVISION D 10/15/15 1 2015 Integrated Device Technology, Inc.8430I-61 DATA SHEET FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes oper- will automatically occur during power-up. The TEST output is ation using a 16MHz crystal. Valid PLL loop divider values for LOW when operating in the parallel input mode. The relationship different crystal or input frequencies are de ned in the Input between the VCO frequency, the crystal frequency and the M fxtal Frequency Characteristics, Table 5, NOTE 1. divider is de ned as follows: fVCO = x M 16 The 8430I-61 features a fully integrated PLL and therefore re- The M value and the required values of M0 through M8 are quires no external components for setting the loop bandwidth. shown in Table 3B, Programmable VCO Frequency Function A parallel-resonant, fundamental crystal is used as the input to Table. Valid M values for which the PLL will achieve lock for a the on-chip oscillator. The output of the oscillator is divided by 16 16MHz reference are de ned as 250 M 500. The frequency fVCO fxtal M prior to the phase detector. With a 16MHz crystal, this provides out is de ned as follows: fout x = = N 16 N a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 500MHz. The output of the M divider is Serial operation occurs when nP LOAD is HIGH and S LOAD also applied to the phase detector. is LOW. The shift register is loaded by sampling the S DATA bits with the rising edge of S CLOCK. The contents of the shift The phase detector and the M divider force the VCO output register are loaded into the M divider and N output divider when frequency to be M times the reference frequency by adjusting S LOAD transitions from LOW-to-HIGH. The M divide and N the VCO control voltage. Note that for some values of M (either output divide values are latched on the HIGH-to-LOW transition too high or too low), the PLL will not achieve lock. The output of S LOAD. If S LOAD is held HIGH, data at the S DATA input is of the VCO is scaled by a divider prior to being sent to each of passed directly to the M divider and N output divider on each ris- the LVPECL output buffers. The divider provides a 50% output ing edge of S CLOCK. The serial mode can be used to program duty cycle. the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The programmable features of the 8430I-61 support two input modes and to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP LOAD input is initially LOW. The data on inputs M0 through T1 T0 TEST Output M8 and N0 through N2 is passed directly to the M divider and N 0 0 LOW output divider. On the LOW-to-HIGH transition of the nP LOAD input, the data is latched and the M divider remains loaded until 0 1 S Data, Shift Register Input the next LOW transition on nP LOAD or until a serial event 1 0 Output of M divider occurs. As a result, the M and N bits can be hard-wired to set the M divider and N output divider to a speci c default state that 1 1 CMOS Fout FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS 500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL 2 REVISION D 10/15/15 LVPECL FREQUENCY SYNTHESIZER