nQ3 XTAL1 Q3 XTAL2 nQ2 nP LOAD VCO SEL Q2 M0 nQ1 M1 Q1 nQ0 M2 M3 Q0 DATA SHEET ICS84314 Integrated ICS84314 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY Circuit 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL Systems, Inc. SYNTHESIZER W/FANOUT BUFFER FREQUENCY SYNTHESIZER W/FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS84314 is a general purpose quad output Fully integrated PLL ICS frequency synthesizer and a member of the 4 differential 3.3V or 2.5V LVPECL outputs HiPerClockS HiPerClock S family of High Performance Clock Solutions from ICS. When the device uses par- Selectable crystal oscillator interface allel loading, the M bits are programmable and or LVCMOS TEST CLK input the output divider is hard-wired for divide by 2 thus providing Output frequency range: 62.5MHz to 350MHz a frequency range of 125MHz to 350MHz. In serial program- ming mode, the M bits are programmable and the output di- VCO range: 250MHz to 700MHz vider can be set for either divide by 2 or divide by 4, providing Parallel interface for programming counter a frequency range of 62.5MHz to 350MHz. The low cycle- and output dividers during power-up cycle jitter and broad frequency range of the ICS84314 make it an ideal clock generator for a variety of demanding applica- Serial 3 wire interface tions which require high performance. Cycle-to-cycle jitter: 23ps (typical) Output skew: 16ps (typical) Output duty cycle: 49% < odc < 51%, fout 125MHz Full 3.3V or mixed 3.3V core, 2.5V operating supply 0C to 85C ambient operating temperature Lead-Free package available BLOCK DIAGRAM PIN ASSIGNMENT VCO SEL 32 31 30 29 28 27 26 25 XTAL SEL M4 1 24 TEST CLK TEST CLK 0 M5 2 23 XTAL SEL M6 3 22 XTAL1 VCCA 1 OSC M7 4 21 S LOAD XTAL2 ICS84314 M8 5 20 S DATA 16 VEE 6 19 S CLOCK VCC 7 18 MR VCCO 8 17 VCCO PLL Q0 PHASE DETECTOR 9 10 11 12 13 14 15 16 nQ0 Q1 MR 0 nQ1 VCO 2 4 Q2 M 1 nQ2 2 Q3 32-Lead LQFP nQ3 7mm x 7mm x 1.4mm package body S LOAD Y Package CONFIGURATION S DATA Top View INTERFACE S CLOCK LOGIC nP LOAD M0:M8 84314AY www.icst.com/products/hiperclocks.html REV. C JANUARY 27, 2005 IDT / ICS 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER ICS84314 1 1ICS84314 Integrated ICS84314 Circuit 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER TSD Systems, Inc. FREQUENCY SYNTHESIZER W/FANOUT BUFFER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes nP LOAD input is initially LOW. The data on inputs M0 through operation using a 16MHz crystal. Valid PLL loop divider M8 is passed directly to the M divider. On the LOW-to-HIGH tran- values for different crystal or input frequencies are defined sition of the nP LOAD input, the data is latched and the M divider in the Input Frequency Characteristics, Table 5, NOTE 1. remains loaded until the next LOW transition on nP LOAD or until a serial event occurs. As a result, the M bits can be hardwired to The ICS84314 features a fully integrated PLL and there- set the M divider to a specific default state that will automatically fore requires no external components for setting the loop occur during power-up. In parallel mode, the N output divider is bandwidth. A parallel-resonant, fundamental crystal is used set to 2. In serial mode, the N output divider can be set for either as the input to the on-chip oscillator. The output of the os- 2 or 4. The relationship between the VCO frequency, the crys- cillator is divided by 16 prior to the phase detector. With a tal frequency and the M divider is defined as follows: fxtal 16MHz crystal, this provides a 1MHz reference frequency. x 2M fVCO = 16 The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the The M value and the required values of M0 through M8 are shown phase detector. in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16MHz refer- The phase detector and the M divider force the VCO output ence are defined as 125 M 350. The frequency out frequency to be 2M times the reference frequency by ad- is defined as follows: fout = fVCO x 1 = fxtal x 2M x 1 N 16 N justing the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve Serial operation occurs when nP LOAD is HIGH and S LOAD lock. The output of the VCO is scaled by a divider prior to is LOW. The shift register is loaded by sampling the S DATA bits being sent to each of the LVPECL output buffers. The divider with the rising edge of S CLOCK. The contents of the shift regis- provides a 50% output duty cycle. ter are loaded into the M divider and N output divider when S LOAD transitions from LOW-to-HIGH. The M divide and N out- The programmable features of the ICS84314 support two put divide values are latched on the HIGH-to-LOW transition of input modes to program the M divider. The two input op- S LOAD. If S LOAD is held HIGH, data at the S DATA input is erational modes are parallel and serial. Figure 1 shows passed directly to the M divider and N output divider on each the timing diagram for each mode. In parallel mode, the rising edge of S CLOCK. SERIAL LOADING S CLOCK S DATA *NULL *NULL *NULL *NULL **N M8M7 M6M5 M4M3 M2M1 M0 t t S LOAD S H nP LOAD t S PARALLEL LOADING M0:M8 M nP LOAD t t Time S H FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS TABLE 1. N OUTPUT DIVIDER FUNCTION TABLE (SERIAL LOAD) NeLogic Value Output Divid 0 2 1 4 *NOTE: The NULL timing slot must be observed. **NOTE: N can only be controlled through serial loading. 84314AY www.icst.com/products/hiperclocks.html REV. C JANUARY 27, 2005 2 IDT / ICS 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER ICS84314 2