XTAL IN VEE nP LOAD nFOUT0 VCO SEL FOUT0 M0 VCCO M1 nFOUT1 M2 FOUT1 M3 VCC M4 TEST 700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL ICS8432-51 LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8432-51 is a general purpose, dual output Crystal-to- Dual differential 3.3V LVPECL outputs 3.3V Differential LVPECL High Frequency Synthesizer. The Selectable crystal oscillator interface or ICS8432-51 has a selectable REF CLK or crystal input. The LVCMOS/LVTTL REF CLK VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of Output frequency range: 31.25MHz to 700MHz the input reference or crystal frequency. The VCO and output Crystal input frequency range: 12MHz to 25MHz frequency can be programmed using the serial or parallel inter- face to the configuration logic. The low phase noise character- VCO range: 250MHz to 700MHz istics of the ICS8432-51 make it an ideal clock source for Giga- Parallel or serial interface for programming counter and bit Ethernet, Fibre Channel 1 and 2, and Infiniband applica- output dividers tions. RMS period jitter: 3.5ps (maximum) Cycle-to-cycle jitter: 25ps (maximum) 3.3V supply voltage 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Replaces the ICS8432-01 BLOCK DIAGRAM PIN ASSIGNMENT 32 31 30 29 28 27 26 25 VCO SEL M5 1 24 XTAL OUT XTAL SEL M6 2 23 REF CLK REF CLK 0 M7 3 22 XTAL SEL XTAL1 M8 4 21 VCCA 1 OSC ICS8432-51 N0 5 20 S LOAD XTAL2 N1 6 19 S DATA nc 7 18 S CLOCK 8 17 MR VEE PLL 9 10 11 12 13 14 15 16 PHASE DETECTOR 1 MR 0 VCO 2 FOUT0 4 nFOUT0 M 1 8 FOUT1 32-Lead LQFP nFOUT1 7mm x 7mm x 1.4mm package body S LOAD CONFIGURATION Y Package S DATA INTERFACE TEST Top View S CLOCK LOGIC nP LOAD 32-Lead VFQFN M0:M8 5mm x 5mm x 0.925mm package body K Package N0:N1 Top View IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER 1 ICS8432CY-51 REVISION F NOVEMBER 13, 2012ICS8432-51 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes opera- N output divider to a specific default state that will automatically tion using a 25MHz crystal. Valid PLL loop divider values for dif- occur during power-up. The TEST output is LOW when operating ferent crystal or input frequencies are defined in the Input in the parallel input mode. The relationship between the VCO Frequency Characteristics, Table 5, NOTE 1. frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The ICS8432-51 features a fully integrated PLL and therefore, requires no external components for setting the loop bandwidth. The M value and the required values of M0 through M8 are shown A fundamental crystal is used as the input to the on-chip oscilla- in Table 3B, Programmable VCO Frequency Function Table. tor. The output of the oscillator is fed into the phase detector. Valid M values for which the PLL will achieve lock for a 25MHz A 25MHz crystal provides a 25MHz phase detector reference reference are defined as 10 M 28. The frequency out is de- frequency. The VCO of the PLL operates over a range of 250MHz fined as follows: FOUT = fVCO = fxtal x M N N to 700MHz. The output of the M divider is also applied to the phase detector. Serial operation occurs when nP LOAD is HIGH and S LOAD is LOW. The shift register is loaded by sampling the S DATA bits The phase detector and the M divider force the VCO output fre- with the rising edge of S CLOCK. The contents of the shift reg-ister quency to be M times the reference frequency by adjusting the are loaded into the M divider and N output divider when S LOAD VCO control voltage. Note that for some values of M (either too high transitions from LOW-to-HIGH. The M divide and N output divide or too low), the PLL will not achieve lock. The output of the VCO is values are latched on the HIGH-to-LOW transition of S LOAD. If scaled by a divider prior to being sent to each of the LVPECL output S LOAD is held HIGH, data at the S DATA input is passed directly buffers. The divider provides a 50% output duty cycle. to the M divider and N output divider on each ris-ing edge of S CLOCK. The serial mode can be used to program the M and N The programmable features of the ICS8432-51 support two in- bits and test bits T1 and T0. The internal registers T0 and T1 deter- put modes to program the M divider and N output divider. The mine the state of the TEST output as follows: two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP LOAD T1 T0 TEST Output input is initially LOW. The data on inputs M0 through M8 and N0 0 0 LOW and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP LOAD input, the data 0 1 S Data, Shift Register Input is latched and the M divider remains loaded until the next LOW 1 0 Output of M divider transition on nP LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and 1 1 CMOS Fout SERIAL LOADING S CLOCK T1 T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 S DATA t t S H S LOAD t nP LOAD S PARALLEL LOADING M0:M8, N0:N1 M, N nP LOAD t t S H S LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER 2 ICS8432CY-51 REVISION F NOVEMBER 13, 2012