nCLK VEE nP LOAD nFOUT0 VCO SEL FOUT0 M0 VCCO M1 nFOUT1 M2 FOUT1 M3 VCC TEST M4 700MHZ, DIFFERENTIAL-TO-3.3V ICS8432-101 LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8432-101 is a general purpose, dual out- Dual differential 3.3V LVPECL outputs ICS put Differential-to-3.3V LVPECL high frequency Selectable CLK, nCLK or LVCMOS/LVTTL TEST CLK HiPerClockS synthesizer and a member of the HiPerClockS family of High Performance Clock Solutions from TEST CLK can accept the following input levels: ICS. The ICS8432-101 has a selectable TEST CLK LVCMOS or LVTTL or CLK, nCLK inputs. The TEST CLK input accepts LVCMOS CLK, nCLK pair can accept the following differential or LVTTL input levels and translates them to 3.3V LVPECL lev- input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL els. The CLK, nCLK pair can accept most standard differen- tial input levels. The VCO operates at a frequency range of CLK, nCLK or TEST CLK maximum input frequency: 40MHz 250MHz to 700MHz. The VCO frequency is programmed in Output frequency range: 25MHz to 700MHz steps equal to the value of the input differential or single ended reference frequency. The VCO and output frequency can be VCO range: 250MHz to 700MHz programmed using the serial or parallel interfaces to the con- Accepts any single-ended input signal on CLK input with figuration logic. The low phase noise characteristics of the resistor bias on nCLK input ICS8432-101 makes it an ideal clock source for Gigabit Ethernet and SONET applications. Parallel interface for programming counter and output dividers RMS period jitter: 5ps (maximum) Cycle-to-cycle jitter: 25ps (maximum) 3.3V supply voltage 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT VCO SEL CLK SEL TEST CLK 0 32 31 30 29 28 27 26 25 CLK 1 M5 1 24 CLK nCLK M6 2 23 TEST CLK M7 3 22 CLK SEL M8 4 21 VCCA ICS8432-101 N0 5 20 S LOAD PLL N1 6 19 S DATA PHASE DETECTOR nc 7 18 S CLOCK MR 0 VEE 8 17 MR 1 VCO FOUT0 2 nFOUT0 9 10 11 12 13 14 15 16 M 4 1 FOUT1 8 nFOUT1 S LOAD CONFIGURATION S DATA TEST INTERFACE S CLOCK nP LOAD LOGIC 32-Lead LQFP 7mm x 7mm x 1.4mm package body M0:M8 Y Package N0:N1 Top View IDT / ICS 700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER 1 ICS8432DY-101 REV. C APRIL 10, 2007ICS8432-101 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes opera- event occurs. As a result, the M and N bits can be hardwired to tion using a 25MHz clock input. Valid PLL loop divider values set the M divider and N output divider to a specific default state for different input frequencies are defined in the Input Frequency that will automatically occur during power-up. The TEST output Characteristics, Table 5, NOTE 1. is LOW when operating in the parallel input mode. The relation- ship between the VCO frequency, the input frequency and the M The ICS8432-101 features a fully integrated PLL and there- divider is defined as follows: fVCO = f x M IN fore requires no external components for setting the loop band- width. A differential clock input is used as the input to the The M value and the required values of M0 through M8 are ICS8432-101. This input is fed into the phase detector. A 25MHz shown in Table 3B, Programmable VCO Frequency Function clock input provides a 25MHz phase detector reference fre- Table. Valid M values for which the PLL will achieve lock for a quency. The VCO of the PLL operates over a range of 250MHz 25MHz reference are defined as 8 M 28. The frequency out to 700MHz. The output of the M divider is also applied to the is defined as follows: fOUT = fVCO = f x M IN NN phase detector. Serial operation occurs when nP LOAD is HIGH and S LOAD is The phase detector and the M divider force the VCO output LOW. The shift register is loaded by sampling the S DATA frequency to be M times the reference frequency by adjusting bits with the rising edge of S CLOCK. The contents of the shift reg- the VCO control voltage. Note, that for some values of M (ei- ister are loaded into the M divider and N output divider when S LOAD ther too high or too low), the PLL will not achieve lock. The transitions from LOW-to-HIGH. The M divide and N output divide output of the VCO is scaled by a divider prior to being sent to values are latched on the HIGH-to-LOW transition of S LOAD. If each of the LVPECL output buffers. The divider provides a 50% S LOAD is held HIGH, data at the S DATA input is passed directly output duty cycle. to the M divider and N output divider on each rising edge of S CLOCK. The serial mode can be used to The programmable features of the ICS8432-101 support two in- program the M and N bits and test bits T1 and T0. The internal put modes to program the PLL M divider and N output divider. registers T0 and T1 determine the state of the TEST output as fol- The two input operational modes are parallel and serial. Figure1 lows: T1 T0 TEST Output shows the timing diagram for each mode. In parallel mode, the 00 LOW nP LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and 0 1 S Data, Shift Register Input N output divider. On the LOW-to-HIGH transition of the 1 0 Output of M divider nP LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP LOAD or until a serial 1 1 CMOS Fout SERIAL LOADING S CLOCK S DATA T1 T0 *NULL N1 N0 M8 M7M6 M5M4 M3M2 M1M0 t t S H S LOAD nP LOAD t S PARALLEL LOADING M, N M0:M8, N0:N1 nP LOAD t t S H S LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. IDT / ICS 700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER 2 ICS8432DY-101 REV. C APRIL 10, 2007