nCLK VEE nP LOAD nFOUT0 VCO SEL FOUT0 M0 VCCO M1 nFOUT1 M2 FOUT1 M3 VCC M4 TEST 700MHz, Differential-to-3.3V LVPECL 8432I-101 Data Sheet Frequency Synthesizer GENERAL DESCRIPTION FEATURES The 8432I-101 is a general purpose, dual out- Dual differential 3.3V LVPECL outputs put Differential-to-3.3V LVPECL high frequency Selectable CLK, nCLK or LVCMOS/LVTTL TEST CLK synthesizer and a member of the family of High Performance Clock Solutions from TEST CLK can accept the following input levels: IDT. The 8432I-101 has a selectable TEST CLK or CLK, LVCMOS or LVTTL nCLK inputs. The TEST CLK input accepts LVCMOS or CLK, nCLK pair can accept the following differential LVTTL input levels and translates them to 3.3V LVPECL input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL levels. The CLK, nCLK pair can accept most standard dif- ferential input levels. The VCO operates at a frequency CLK, nCLK or TEST CLK maximum input frequency: 40MHz range of 250MHz to 700MHz. The VCO frequency is pro- Output frequency range: 25MHz to 700MHz grammed in steps equal to the value of the input differential or single ended reference frequency. The VCO and output VCO range: 250MHz to 700MHz frequency can be programmed using the serial or parallel Accepts any single-ended input signal on CLK input with resis- interfaces to the configuration logic. The low phase noise tor bias on nCLK input characteristics of the 8432I-101 makes it an ideal clock source for Gigabit Ethernet and SONET applications. Parallel interface for programming counter and output dividers RMS period jitter: 5ps (maximum) Cycle-to-cycle jitter: 25ps (maximum) 3.3V supply voltage -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT 32 31 30 29 28 27 26 25 M5 1 24 CLK M6 2 23 TEST CLK M7 3 22 CLK SEL M8 4 21 VCCA ICS8432I-101 N0 5 20 S LOAD N1 6 19 S DATA nc 7 18 S CLOCK 8 MR VEE 17 9 10 11 12 13 14 15 16 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 2016 Integrated Device Technology, Inc 1 Revision C January 8, 20168432I-101 Data Sheet FUNCTIONAL DESCRIPTION set the M divider and N output divider to a speci c default state NOTE: The functional description that follows describes operation that will automatically occur during power-up. The TEST output is using a 25MHz clock input. Valid PLL loop divider values for different LOW when operating in the parallel input mode. The relationship input frequencies are de ned in the Input Frequency Characteristics, between the VCO frequency, the input frequency and the M divider Table 5, NOTE 1. is de ned as follows: fVCO = f x M IN The 8432I-101 features a fully integrated PLL and therefore The M value and the required values of M0 through M8 are shown requires no external components for setting the loop band- in Table 3B, Programmable VCO Frequency Function Table. Valid width. A differential clock input is used as the input to the 8432I- M values for which the PLL will achieve lock for a 25MHz reference 101. This input is fed into the phase detector. A 25MHz clock input are de ned as 8 M 28. The frequency out is de ned as follows: provides a 25MHz phase detector reference frequency. The VCO of fOUT = fVCO = f x M the PLL operates over a range of 250MHz to 700MHz. The output IN N N of the M divider is also applied to the phase detector. Serial operation occurs when nP LOAD is HIGH and S LOAD is LOW. The shift register is loaded by sampling the S DATA The phase detector and the M divider force the VCO output bits with the rising edge of S CLOCK. The contents of the shift frequency to be M times the reference frequency by adjust- register are loaded into the M divider and N output divider when ing the VCO control voltage. Note, that for some values of M S LOAD transitions from LOW-to-HIGH. The M divide and N out- (either too high or too low), the PLL will not achieve lock. The put divide values are latched on the HIGH-to-LOW transition of output of the VCO is scaled by a divider prior to being sent S LOAD. If S LOAD is held HIGH, data at the S DATA input is to each of the LVPECL output buffers. The divider provides a passed directly to the M divider and N output divider on each rising 50% output duty cycle. edge of S CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 The programmable features of the 8432I-101 support two and T1 determine the state of the TEST output as follows: input modes to program the PLL M divider and N output divider. The two input operational modes are parallel and serial. Figure1 shows the timing diagram for each mode. In parallel mode, the T1 T0 TEST Output nP LOAD input is initially LOW. The data on inputs M0 through 0 0 LOW M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the 0 1 S Data, Shift Register Input nP LOAD input, the data is latched and the M divider remains 1 0 Output of M divider loaded until the next LOW transition on nP LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to 1 1 CMOS Fout FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. 2016 Integrated Device Technology, Inc 2 Revision C January 8, 2016