VEE TEST VCC VEE nFOUT FOUT VCC 700MHz, Low Jitter, Crystal-to-3.3V 84330C Differential LVPECL Frequency DATA SHEET General Description Features The 84330C is a general purpose, single output high frequency Fully integrated PLL, no external loop filter requirements synthesizer. The VCO operates at a frequency range of 250MHz to One differential 3.3V LVPECL output 700MHz. The VCO and output frequency can be programmed using Crystal oscillator interface: 10MHz to 25MHz the serial or parallel interfaces to the configuration logic. The output Output frequency range: 31.25MHz to 700MHz can be configured to divide the VCO frequency by 1, 2, 4, and 8. Output frequency steps as small as 250kHz to 2MHz can be achieved VCO range: 250MHz to 700MHz using a 16MHz crystal depending on the output divider settings. Parallel or serial interface for programming M and N dividers during power-up RMS period jitter: 5ps (maximum) Cycle-to-cycle jitter: 40ps (maximum) 3.3V supply voltage 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Pin Assignments 25 24 23 22 21 20 19 26 N1 S CLOCK 18 S DATA 27 17 N0 ICS84330C S LOAD 16 M8 28 28 Lead PLCC V Package M7 VCCA 1 15 11.6mm x 11.4mm x 4.1mm M6 FREF EXT 2 14 package body Top View XTAL SEL 3 13 M5 Block Diagram XTAL1 4 12 M4 Pullup 5 6 7 8 9 10 11 OE XTAL1 1 OSC XTAL2 Pulldown FREF EXT 0 16 Pullup XTAL SEL 32 31 30 29 28 27 26 25 S CLOCK 1 nc 24 PLL 2 S DATA 23 N1 84330C 2 PHASE DETECTOR 4 S LOAD 3 N0 22 32 Lead LQFP 1 8 FOUT M8 VCCA Y Package VCO 4 21 1 nFOUT 7mm x 7mm x 1.4mm VCCA M7 0 5 20 M 2 package body FREF EXT 6 M6 19 Top View XTAL SEL 7 M5 18 S LOAD Pulldown CONFIGURATION Pulldown S DATA XTAL1 8 M4 17 TEST Pulldown INTERFACE S CLOCK 9 10 11 12 13 14 15 16 Pullup LOGIC nP LOAD Pullup M0:M8 Pullup N0:N1 84330C Rev D 4/22/15 1 2015 Integrated Device Technology, Inc. XTAL2 VCC XTAL2 OE FOUT OE nP LOAD nFOUT nP LOAD M0 VEE M0 VCC M1 M1 M2 VCC M2 M3 TEST M3 nc VEE84330C DATA SHEET Functional Description NOTE: The functional description that follows describes operation transition of the nP LOAD input, the data is latched and the M divider using a 16MHz crystal. Valid PLL loop divider values for different remains loaded until the next LOW transition on nP LOAD or until a crystal or input frequencies are defined in the Input Frequency serial event occurs. The TEST output is Mode 000 (shift register out) Characteristics, Table 6, NOTE 1. when operating in the parallel input mode. The relationship between The 84330C features a fully integrated PLL and therefore requires no the VCO frequency, the crystal frequency and the M divider is defined external components for setting the loop bandwidth. A quartz crystal as follows: is used as the input to the on-chip oscillator. The output of the fVCO = fXTAL x 2M oscillator is divided by 16 prior to the phase detector. With a 16MHz 16 crystal, this provides a 1MHz reference frequency. The VCO of the The M value and the required values of M0 through M8 are shown in PLL operates over a range of 250MHz to 700MHz. The output of the Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock are defined as 125 M M divider is also applied to the phase detector. 350. The frequency out is defined as follows: The phase detector and the M divider force the VCO output fre- fout = fVCO = fXTAL x 2M quency to be 2M times the reference frequency by adjusting the VCO N16 N control voltage. Note that for some values of M (either too high or too Serial operation occurs when nP LOAD is HIGH and S LOAD is low), the PLL will not achieve lock. The output of the VCO is scaled LOW. The shift register is loaded by sampling the S DATA bits with by a divider prior to being sent to each of the LVPECL output buffers. the rising edge of S CLOCK. The contents of the shift register are The divider provides a 50% output duty cycle. loaded into the M divider when S LOAD transitions from The programmable features of the 84330C support two input modes LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S LOAD. If S LOAD is held HIGH, to program the M divider and N output divider. The two input data at the S DATA input is passed directly to the M divider on each operational modes are parallel and serial. Figure 1 shows the timing rising edge of S CLOCK. The serial mode can be used to program diagram for each mode. In parallel mode the nP LOAD input is LOW. the M and N bits and test bits T2:T0. The internal registers T2:T0 The data on inputs M0 through M8 and N0 through N1 is passed determine the state of the TEST output as follows in the table below: directly to the M divider and N output divider. On the LOW-to-HIGH T2 T1 T0 TEST Output f OUT 0 0 0 Shift Register Out f OUT 00 1 HIGH f OUT 0 1 0 PLL Reference XTAL 16 f OUT 0 1 1 (VCO M)/2 (non 50% Duty Cycle M Divider) f OUT 10 0 f , LVCMOS Output Frequency < 200MHz f OUT OUT 10 1 LOW f OUT 1 1 0 (S CLOCK M)/2 (non 50% Duty Cycle M Divider) S CLOCK N Divider 11 1 f 4 f OUT OUT SERIAL LOADING S CLOCK T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 S DATA t t S H S LOAD t nP LOAD S PARALLEL LOADING M, N M0:M8, N0:N1 nP LOAD t t S H nP LOAD Time Figure 1. Parallel & Serial Load Operations Rev D 4/22/15 2 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER