VEE FemtoClock NG Crystal-to-3.3V 843N252-45 LVPECL Frequency Synthesizer Data Sheet General Description Features The 843N252-45 is a 1 LVPECL and 1 LVCMOS output Synthesizer Fourth generation FemtoClock Next Generation (NG) technology optimized to generate Ethernet reference clock frequencies. The One differential 3.3V LVPECL output and one LVCMOS/LVTTL device uses IDTs fourth generation FemtoClock NG technology for output an optimum of high clock frequency and low phase noise Crystal oscillator interface designed for a 25MHz parallel resonant performance, combined with a low power consumption and high crystal power supply noise rejection. Using a 25MHz parallel resonant A 25MHz crystal generates output frequencies of: 156.25MHz and crystal, the following frequencies can be generated: 156.25MHz and 125MHz 125MHz. With a very low phase noise VCO it is targeted to achieve VCO frequency: 625MHz 0.4ps or lower typical rms phase jitter, easily meeting Ethernet jitter RMS Phase Jitter 156.25MHz, (12kHz 20MHz) using a requirements. The 843N252-45 is packaged in a small 16-pin 25MHz crystal: 0.33ps (typical) TSSOP package. RMS Phase Jitter 125MHz, (12kHz 20MHz) using a 25MHz crystal: 0.39ps (typical) Power supply noise rejection PSNR: -60dB (typical) Full 3.3V supply mode 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment CLK ENA 1 16 CLK ENB Pullup CLK ENA VEE 2 15 VEE QA 3 14 QB QA 25MHz 5 XTAL IN VCCOA 4 13 nQB PFD FemtoClock NG OSC nc 5 12 VCC & VCO 625MHz QB nc LPF 6 11 XTAL IN XTAL OUT 4 VCCA 7 XTAL OUT nQB 10 VCC 8 9 Feedback Divider 25 843N252-45 Pullup CLK ENB 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package 2016 Integrated Device Technology, Inc 1 Revision A April 20, 2016843N252-45 Data Sheet Table 1. Pin Descriptions Number Name Type Description 1 CLK ENA Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels. See Table 3A. 2, 9, 15 V Power Negative supply pins. EE 3 QA Output Single-ended clock output. LVCMOS/LVTTL interface levels. 4V Power Output supply pin for QA output. CCOA 5, 6 nc Unused No connect. 7V Power Analog supply pin. CCA 8, 12 V Power Power supply pin. CC 10 XTAL OUT Input Crystal oscillator interface XTAL IN is the input, XTAL OUT is the output. 11 XTAL IN 13, 14 nQB, QB Output Differential output pair. LVPECL interface levels. 16 CLK ENB Input Pullup Clock enable pin. LVCMOS/LVTTL interface levels. See Table 3B. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN C Power Dissipation Capacitance V = V = 3.465V 7 pF PD CC CCO A R Input Pullup Resistor 51 k PULLUP R Output Impedance QA V = 3.465V 15 OUT CCO A Function Tables Table 3A. CLK ENA Function Table Table 3B. CLK ENB Function Table Input Outputs Input Outputs CLK ENA QA CLK ENB QB nQB 0 High-Impedance 0HIGH LOW 1 Active 1 Active Active 2016 Integrated Device Technology, Inc 2 Revision A April 20, 2016