FemtoClock Crystal-to-3.3V LVDS 844003 Frequency Synthesizer Datasheet General Description Features The 844003 is a three differential output LVDS Synthesizer designed Three LVDS outputs on two banks, A Bank with one LVDS pair and B Bank with two LVDS output pairs to generate Ethernet reference clock frequencies. Using a 31.25MHz or 26.041666MHz, 18pF parallel resonant crystal, the following Using a 31.25MHz or 26.041666MHz crystal, the two output banks can be independently set for 625MHz, 312.5MHz, frequencies can be generated based on the settings of four 156.25MHz or 125MHz frequency select pins (DIV SEL A1:A0 , DIV SEL B1:B0 ): 625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 844003 has two output Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input banks, Bank A with one differential LVDS output pair and Bank B with two differential LVDS output pairs. VCO range: 560MHz to 700MHz The two banks have their own dedicated frequency select pins and RMS phase jitter 156.25MHz (1.875MHz - 20MHz): 0.63ps (typical) can be independently set for the frequencies mentioned above. The 3.3V output supply mode rd 844003 uses IDTs 3 generation low phase noise VCO technology 0C to 70C ambient operating temperature and can achieve 1ps or lower typical rms phase jitter, easily meeting Available in lead-free (RoHS 6) packaging Ethernet jitter requirements. The 844003 is packaged in a small 24-pin TSSOP package. Pin Assignment DIV SELB0 1 24 DIV SELB1 VCO SEL 2 23 V DDO B MR 3 22 QB0 V 4 21 nQB0 DDO A QA0 5 20 QB1 nQA0 6 19 nQB1 OEB 7 18 XTAL SEL OEA 8 17 TEST CLK FB DIV 9 16 XTAL IN V 10 15 XTAL OUT DDA V 11 14 GND DD Block Diagram DIV SELA0 12 13 DIV SELA1 844003 24-Lead TSSOP Pullup OEA 4.40mm x 7.8mm x 0.92mm Pulldown:Pullup package body DIV SELA 1:0 Pullup VCO SEL G Package QA0 0 0 1 Top View Pulldown 0 1 2 (default) nQA0 0 TEST CLK 0 1 0 4 1 1 5 XTAL IN Phase 1 OSC 1 VCO Detector XTAL OUT Pullup QB0 XTAL SEL FB DIV 0 0 1 nQB0 0 1 2 0 = 20 (default) 1 0 4 (default) 1 = 24 QB1 1 1 5 Pulldown nQB1 FB DIV Pullup:Pulldown DIV SELB 1:0 Pulldown MR Pullup OEB 2016 Integrated Device Technology, Inc. 1 January 29, 2016844003 Datasheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 DIV SELB0 Input Pulldown Division select pin for Bank B. LVCMOS/LVTTL interface levels. See Table 3C. VCO select pin. When Low, the PLL is bypassed and the crystal reference or TEST CLK (depending on XTAL SEL setting) are passed directly to the output 2 VCO SEL Input Pullup dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. 3 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. Has an internal pulldown resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. 4V Power Output supply pin for Bank A outputs. DDO A 5 QA0 Output Differential output pair. LVDS interface levels. 6 nQA0 Output Differential output pair. LVDS interface levels. Output enable Bank B. Active High outputs are enable. When logic HIGH, the output pairs on Bank B are enabled. When logic LOW, the output pairs are in a 7 OEB Input Pullup high impedance state. Has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3F. Output enable Bank A. Active High output enable. When logic HIGH, the output pair in Bank A is enabled. When logic LOW, the output pair is in a high 8 OEA Input Pullup impedance state. Has an internal pullup resistor so the default power-up state of output is enabled. LVCMOS/LVTTL interface levels. See Table 3E. Feedback divide select. When Low (default), the feedback divider is set for 20. 9 FB DIV Input Pulldown When HIGH, the feedback divider is set for 24. See Table 3D LVCMOS/LVTTL interface levels. 10 V Power Analog supply pin. DDA 11 V Power Core supply pin. DD 12 DIV SELA0 Input Pullup Division select pin for Bank A. LVCMOS/LVTTL interface levels. See Table 3C. 13 DIV SELA1 Input Pulldown Division select pin for Bank A. LVCMOS/LVTTL interface levels. See Table 3C. 14 GND Power Power supply ground. 15 XTAL OUT Output Parallel resonant crystal interface. XTAL OUT is the output. Parallel resonant crystal interface. XTAL IN is the input. XTAL IN is also the 16 XTAL IN Input overdrive pin if you want to overdrive the crystal circuit with a single-ended reference clock. Single-ended reference clock input. Has an internal pulldown resistor to pull to 17 TEST CLK Input Pulldown low state by default. Can leave floating if using the crystal interface. LVCMOS/LVTTL interface levels. Crystal select pin. Selects between the single-ended TEST CLK or crystal 18 XTAL SEL Input Pullup interface. Has an internal pullup resistor so the crystal interface is selected by default. LVCMOS/LVTTL interface levels. 19 nQB1 Output Differential output pair. LVDS interface levels. 20 QB1 Output Differential output pair. LVDS interface levels. 2016 Integrated Device Technology, Inc. 2 January 29, 2016