REF CLK DIV SELA1 FEMTOCLOCKS Crystal-to-LVDS 844003BI-01 Frequency Synthesizer DATASHEET General Description Features The 844003BI-01 is a 3 differential output LVDS Synthesizer Three differential LVDS output pairs on two banks, Bank A with one LVDS pair and Bank B with two LVDS output pairs designed to generate Ethernet reference clock frequencies. Using a 19.53125MHz or 25MHz, 18pF parallel resonant crystal, the Using a 19.53125MHz or 25MHz crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz following frequencies can be generated based on the settings of 4 or 125MHz frequency select pins (DIV SELA 1:0 , DIV SELB 1:0 ): 625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 844003BI-01 has 2 Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input output banks, Bank A with 1 differential LVDS output pair and Bank B with 2 differential LVDS output pairs. VCO range: 490MHz - 680MHz The two banks have their own dedicated frequency select pins and RMS phase jitter 156.25MHz (1.875MHz 20MHz): 0.56ps (typical) can be independently set for the frequencies mentioned above. rd The 844003BI-01 uses IDTs 3 generation low phase noise VCO Full 3.3V supply mode technology and can achieve 1ps or lower typical rms phase jitter, -40C to 85C ambient operating temperature easily meeting Ethernet jitter requirements. The 844003BI-01 is Available in lead-free (RoHS 6) package packaged in a small 24-pin TSSOP package. Pin Assignment DIV SELB1 DIV SELB0 1 24 VCO SEL 2 23 VDDO B MR 3 22 QB0 V DDO A 4 21 nQB0 QA0 5 20 QB1 nQA0 6 19 nQB1 XTAL SEL OEB 7 18 OEA 8 17 9 XTAL IN FB DIV 16 XTAL OUT V 10 15 DDA V DD 11 14 GND DIV SELA0 12 13 Block Diagram 24-Lead TSSOP, E-Pad Pullup 4.40mm x 7.8mm x 0.925mm OEA package body Pullup DIV SELA 1:0 G Package Pullup VCO SEL QA0 0 0 1 Pulldown QA0 0 1 2 REF CLK 0 0 1 0 3 1 1 4 (default) XTAL IN Phase VCO OSC 1 1 Detector XTAL OUT Pullup QB0 XTAL SEL FB DIV 0 0 2 QB0 0 1 4 0 = 25 (default) 1 0 5 QB1 1 = 32 1 1 8 (default) Pulldown FB DIV QB1 Pullup DIV SELB 1:0 Pulldown MR Pullup OEB 844003BI-01 Rev B 12/18/14 1 2014 Integrated Device Technology, Inc.844003BI-01 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1, DIV SELB0, Division select pin for Bank B. Default = HIGH. Input Pullup 24 DIV SELB1 LVCMOS/LVTTL interface levels. See Table 3B. VCO select pin. When Low, the PLL is bypassed and the crystal reference or REF CLK (depending on XTAL SEL setting) are passed directly to the output 2 VCO SEL Input Pullup dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. 3 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. Has an internal pulldown resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. 4V Power Output supply pin for Bank A outputs. DDO A 5, 6 QA0, nQA0 Output Differential output pair. LVDS interface levels. Output enable Bank B. Active High outputs are enable. When logic HIGH, the output pairs on Bank B are enabled. When logic LOW, the output pairs are in a 7 OEB Input Pullup high impedance state. Has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3E. Output enable Bank A. Active High output enable. When logic HIGH, the output pair in Bank A is enabled. When logic LOW, the output pair is in a high 8 OEA Input Pullup impedance state. Has an internal pullup resistor so the default power-up state of output is enabled. LVCMOS/LVTTL interface levels. See Table 3D. Feedback divide select. When Low (default), the feedback divider is set for 25. 9 FB DIV Input Pulldown When HIGH, the feedback divider is set for 32. See Table 3C. LVCMOS/LVTTL interface levels. 10 V Power Analog supply pin. DDA 11 V Power Core supply pin. DD 12, DIV SELA0, Division select pin for Bank A. Default = HIGH. See Table 3A. Input Pullup 13 DIV SELA1 LVCMOS/LVTTL interface levels. 14 GND Power Power supply ground. Parallel resonant crystal interface. XTAL OUT is the output, XTAL IN is the 15, XTAL OUT, Input input. XTAL IN is also the overdrive pin if you want to overdrive the crystal circuit 16 XTAL IN with a single-ended reference clock. Single-ended reference clock input. Has an internal pulldown resistor to pull to 17 REF CLK Input Pulldown low state by default. Can leave floating if using the crystal interface. LVCMOS/LVTTL interface levels. Crystal select pin. Selects between the single-ended REF CLK or crystal 18 XTAL SEL Input Pullup interface. Has an internal pullup resistor so the crystal interface is selected by default. LVCMOS/LVTTL interface levels. 19, 20 nQB1, QB1 Output Differential output pair. LVDS interface levels. 21, 22 nQB0, QB0 Output Differential output pair. LVDS interface levels. Power Output supply pin for Bank B outputs. 23 V DDO B NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. FEMTOCLOCKS CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 2 Rev B 12/18/14