FemtoClock Crystal-to-LVDS Frequency 844004I-104 Synthesizer DATA SHEET General Description Features The 844004I-104 is a 4 output LVDS Synthesizer optimized to Four differential LVDS outputs generate Fibre Channel reference clock frequencies. Using a Selectable crystal oscillator interface or LVCMOS/LVTTL 26.5625MHz 18pF parallel resonant crystal, the following single-ended input frequencies can be generated based on the two frequency select Supports the following output frequencies: 212.5MHz, 187.5MHz, pins (F SEL 1:0 ): 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz 159.375MHz, 106.25MHz and 53.125MHz RD and 53.125MHz. The 844004I-104 uses IDTs 3 generation low VCO range: 560MHz - 680MHz phase noise VCO technology and can achieve <1ps typical rms RMS phase jitter at 212.5MHz (637kHz 10MHz), using a phase jitter, easily meeting Fibre Channel jitter requirements. The 26.5625MHz crystal: <1ps (typical) 844004I-104 is packaged in a 32-pin VFQFN package. Full 3.3V or 2.5V output supply modes -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) packages Frequency Table Inputs Pin Assignment Input F SEL1 F SEL0 M N M/N Output Frequency Divider Divider Divider Frequency (MHz) Value Value Value (MHz) 32 31 30 29 28 27 26 25 Q0 1 Q3 24 212.5 26.5625 0 0 24 3 8 nQ0 2 23 nQ3 ICS844004I-104 (default) MR 3 22 GND 32 Lead VFQFN 26.5625 0 1 24 4 6 159.375 nc nPLL SEL 4 21 5mm x 5mm x 0.925mm 26.5625 1 0 24 6 4 106.25 nc package body nc 5 20 K Package 26.5625 1 1 24 12 2 53.125 nc 6 nXTAL SEL 19 Top View nc 7 18 REF CLK 187.5 23.4375 0 0 24 3 8 (default) nc 8 17 GND 9 10 11 12 13 14 15 16 Block Diagram Pulldown 2 F SEL 1:0 Pulldown nPLL SEL Q0 F SEL 1:0 nQ0 Pulldown 0 0 3 REF CLK 11 1 0 1 4 Q1 26.5625MHz 1 0 6 VCO XTAL IN 1 1 12 Phase nQ1 637.5MHz 0 OSC 0 Detector (w/26.5625MHz Reference) XTAL OUT Q2 Pulldown nXTAL SEL nQ2 Q3 M = 24 (fixed) nQ3 Pulldown MR 844004I-104 Rev A 6/11/15 1 2015 Integrated Device Technology, Inc. VDDA VDDO F SEL0 Q1 VDD nQ1 F SEL1 nc XTAL OUT nc XTAL IN nQ2 nc Q2 nc VDDO844004I-104 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx 3 MR Input Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and REF CLK as input to the dividers. When LOW, 4 nPLL SEL Input Pulldown selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. 5, 6, 7, 8, 15, 16, 20, 21, nc Unused No connect. 28, 29 9V Power Analog supply pin. DDA 10, F SEL0, Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. 12 F SEL1 11 V Power Core supply pin. DD 13, XTAL OUT Input Crystal oscillator interface. XTAL IN is the input, XTAL OUT is the output. 14 XTAL IN 17, 22 GND Power Power supply ground. 18 REF CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels. Selects between crystal or REF CLK inputs as the PLL Reference source. Selects 19 nXTAL SEL Input Pulldown XTAL inputs when LOW. Selects REF CLK when HIGH. LVCMOS/LVTTL interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVDS interface levels. 25, 32 V Power Output supply pins. DDO 26, 27 Q2, nQ2 Output Differential output pair. LVDS interface levels. 30, 31 nQ1, Q1 Output Differential output pair. LVDS interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pulldown Resistor 51 k PULLDOWN Rev A 6/11/15 2 FEMTOCLOCK CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER