FemtoClock Crystal-to-LVDS Frequency ICS844256D Synthesizer w/Integrated Fanout Buffer DATA SHEET General Description Features The ICS844256D is a Crystal-to-LVDS Clock Synthesizer/Fanout Six differential LVDS output pairs Buffer designed for SONET and Gigabit Ethernet applications. The Crystal oscillator interface output frequency can be set using the frequency select pins and a Output frequency range: 62.5MHz - 625MHz 25MHz crystal for Ethernet frequencies, or a 19.44MHz crystal for Crystal input frequency range:15.625MHz - 25.5MHz SONET. The low phase noise characteristics of the ICS844256D make it an ideal clock for these demanding applications. RMS phase jitter 125MHz, using a 25MHz crystal (1.875MHz 20MHz): 0.43ps (typical) Full 3.3V or mixed 3.3V core, 2.5V output supply mode 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Divider Function Table Inputs Function FB SEL N SEL1 N SEL0 M Divider Value N Divider Value M/N Divider Value 000 25 1 25 0 0 1 25 2 12.5 010 25 4 6.25 0 1 1 25 (default) 5 5 100 32 1 32 101 32 2 16 110 32 4 8 111 32 8 4 Block Diagram Pin Assignment Q0 Pullup VDDO 1 24 Q3 PLL BYPASS nQ0 VDDO 2 23 nQ3 Q1 nQ2 3 22 Q4 Q2 4 21 nQ4 1 nQ1 nQ1 5 20 Q5 N Q1 6 19 nQ5 Output Q2 XTAL IN nQ0 7 18 N SEL1 Divider PLL OSC 0 Q0 8 17 GND nQ2 PLL BYPASS 9 16 GND XTAL OUT VDDA 10 15 N SEL0 Q3 VDD 11 14 XTAL OUT nQ3 FB SEL 12 13 XTAL IN M Feedback Q4 ICS844256D Divider nQ4 Pulldown 24-Lead TSSOP, E-Pad FB SEL Pullup 4.40mm x 7.8mm x 0.925mm Q5 N SEL1 package body Pullup N SEL0 nQ5 G Package Top View ICS844256DG REVISION A AUGUST 5, 2010 1 2010 Integrated Device Technology, Inc. ICS844256D Data Sheet FEMTOCLOCK CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 2 V Power Output supply pins. DDO 3, 4 nQ2, Q2 Output Differential output pair. LVDS interface levels. 5, 6 nQ1, Q1 Output Differential output pair. LVDS interface levels. 7, 8 nQ0, Q0 Output Differential output pair. LVDS interface levels. PLL Bypass. When LOW, the output is driven from the VCO output. When HIGH, 9 PLL BYPASS Input Pullup the PLL is bypassed and the output frequency = crystal frequency N output divider. LVCMOS / LVTTL interface levels. Power Analog supply pin. 10 V DDA Power Core supply pin. 11 V DD Feedback and output frequency select pin. LVCMOS/LVTTL interface levels. 12 FB SEL Input Pulldown See Table 3. 13, XTAL IN, Input Crystal oscillator interface. XTAL IN is the input. XTAL OUT is the output. 14 XTAL OUT 15, N SEL0, Feedback and output frequency select pins. LVCMOS/LVTTL interface levels. Input Pullup 18 N SEL1 See Table 3. 16, 17 GND Power Power supply ground. 19, 20 nQ5, Q5 Output Differential output pair. LVDS interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVDS interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4pF C IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN ICS844256DG REVISION A AUGUST 5, 2010 2 2010 Integrated Device Technology, Inc.