XTAL IN GND nP LOAD nFOUT0 VCO SEL FOUT0 M0 V DD M1 M2 M3 V DD M4 TEST 700MHZ, CRYSTAL OSCILLATOR-TO- ICS8442BI DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER DATA SHEET GENERAL DESCRIPTION FEATURES The ICS8442BI is a general purpose, dual output Crystal- Dual differential LVDS outputs to-Differential LVDS High Frequency Synthesizer. Selectable crystal oscillator interface or The ICS8442BI has a selectable TEST CLK or crystal LVCMOS/LVTTL TEST CLK input. The TEST CLK input accepts LVCMOS or LVTTL input levels and translates them to LVDS levels. The VCO operates Output frequency range: 31.25MHz to 700MHz at a frequency range of 250MHz to 700MHz.The VCO Crystal input frequency range: 10MHz to 25MHz frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output VCO range: 250MHz to 700MHz frequency can be programmed using the serial or Parallel or serial interface for programming counter parallelinterface to the configuration logic. The low phase and output dividers noisecharacteristics of the ICS8442BI makes it an ideal clock source for Gigabit Ethernet and Sonet applications. RMS period jitter: 3.5ps (typical) Cycle-to-cycle jitter: 18ps (typical) 3.3V supply voltage -40C to 85C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT VCO SEL XTAL SEL TEST CLK 0 32 31 30 29 28 27 26 25 XTAL IN 1 24 M5 1 XTAL OUT OSC 23 TEST CLK M6 2 XTAL OUT 22 XTAL SEL M7 3 21 V M8 4 DDA ICS8442BI 20 S LOAD N0 5 PLL 19 S DATA N1 6 PHASE DETECTOR 1 18 S CLOCK nc 7 2 17 MR MR GND 8 0 VCO 4 FOUT0 9 14 15 16 8 nFOUT0 M 1 FOUT1 nFOUT1 S LOAD CONFIGURATION S DATA INTERFACE TEST S CLOCK LOGIC nP LOAD 32-Lead LQFP 7mm x 7mm x 1.4mm package body M0:M8 Y Package N0:N1 Top View ICS8442BYI REVISION A NOVEMBER 18, 2013 1ICS8442BI Data Sheet 700MHz, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes op- output divider to a specific default state that will automati- eration using a 25MHz crystal. Valid PLL loop divider values cally occur during power-up. The TEST output is LOW when for different crystal or input frequencies are defined in the In- operating in the parallel input mode. The relationship be- put Frequency Characteristics, Table 5, NOTE 1. tween the VCO frequency, the crystal frequency and the M divider is defined as follows: The ICS8442BI features a fully integrated PLL and there- fVCO = fxtal x M fore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the The M value and the required values of M0 through M8 are on-chip oscillator. The output of the oscillator is fed into the shown in Table 3B, Programmable VCO Frequency Function phase detector. A 25MHz crystal provides a 25MHz phase Table. Valid M values for which the PLL will achieve lock for a detector reference frequency. The VCO of the PLL operates 25MHz reference are defined as 10 M 28. The frequency over a range of 250MHz to 700MHz. The output of the M out is defined as follows: divider is also applied to the phase detector. fVCO = fxtal x M FOUT = N N The phase detector and the M divider force the VCO output fre- Serial operation occurs when nP LOAD is HIGH and S LOAD quency to be M times the reference frequency by adjusting the is LOW. The shift register is loaded by sampling the S DATA VCO control voltage. Note that for some values of M (either too bits with the rising edge of S CLOCK. The contents of the high or too low), the PLL will not achieve lock. The output of the shift register are loaded into the M divider and N output di- VCO is scaled by a divider prior to being sent to each of the vider when S LOAD transitions from LOW-to-HIGH. The M LVDS output buffers. The divider provides a 50% output duty cycle. divide and N output divide values are latched on the HIGH-to- LOW transition of S LOAD. If S LOAD is held HIGH, data at The programmable features of the ICS8442BI support two the S DATA input is passed directly to the M divider and N input modes to program the M divider and N output divider. output divider on each rising edge of S CLOCK. The serial The two input operational modes are parallel and serial. mode can be used to program the M and N bits and test bits Figure 1 shows the timing diagram for each mode. In paral- T1 and T0. The internal registers T0 and T1 determine the state lel mode, the nP LOAD input is initially LOW. The data on of the TEST output as follows: inputs M0 through M8 and N0 and N1 is passed directly to T1 T0 TEST Output the M divider and N output divider. On the LOW-to-HIGH 0 0 LOW transition of the nP LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on 0 1 S Data, Shift Register Input nP LOAD or until a serial event occurs. As a result, the M 1 0 Output of M divider and N bits can be hardwired to set the M divider and N 1 1 CMOS FOUT SERIAL LOADING S CLOCK T1 T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 S DATA t t S H S LOAD nP LOAD t S PARALLEL LOADING M0:M8, N0:N1 M, N nP LOAD t t S H S LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. 2 ICS8442BYI REVISION A NOVEMBER 18, 2013