nc M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 ADR0 ADR1 VDDA Dual Output RF Frequency Synthesizer 844S42I Data Sheet General Description Features The 844S42I is a 3.3V compatible, PLL based clock synthesizer Programmable frequency synthesis optimized for instrumentation, networking and computing applications targeted for clock generation in high-performance instrumentation, 2 networking and computing applications. Using either the serial (I C) 81MHz to 2592MHz synthesized clock output signal or parallel programming interface, the 844S42I enables the Two differential, universal LVDS or LVPECL compatible generation of clock frequencies in the range of 81MHz to 2592MHz. high-frequency outputs The internal crystal oscillator uses the external quartz crystal as the 2 Output frequency programmable through 2-wire I C bus or basis of its frequency reference. Alternatively, a LVCMOS compatible parallel interface clock signal can be used as PLL reference signal. The devices uses On-chip crystal oscillator for reference frequency generation an integer-N synthesizer architecture and is optimized for low-jitter Alternative LVCMOS/LVTTL compatible reference clock input generation. The VCO within the PLL operates over a range of 1296MHz to 2592MHz. Its output is scaled by a divider that is Clock stop and output enable functionality 2 configured by either the I C or parallel interfaces. The crystal PLL lock indicator output (LVCMOS/LVTTL) oscillator frequency f , the PLL pre-divider P, the feedback-divider XTAL LVCMOS/LVTTL compatible control inputs M and the PLL post-divider N determine the output frequency. The Fully integrated PLL feedback path of the PLL is internal. SiGe Technology The PLL post-dividers NA and NB are configured through either the 2 I C or the parallel interfaces, each can provide one of seven division Full 3.3V supply voltage ratios (1, 2, 3, 4, 6, 8, 16). This divider extends the performance of -40C to 85C ambient operating temperature the part while providing a typical 50% duty cycle. The high-frequency Available in a lead-free (RoHS 6) compliant package outputs QA and QB are differential and are capable of driving a pair of transmission lines. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output 2 drivers to minimize noise induced jitter. The serial interface is I C Pin Assignment compatible and provides read and write access to the internal PLL configuration registers. The lock state of the PLL is indicated by the LVCMOS-compatible LOCK DT output. The 844S42I is packaged in a 8mm x 8mm 56-lead VFQFN package. 56 55 54 53 52 51 50 49 48 47 46 45 44 43 GND 1 42 nc nc 2 41 V DDOA 3 40 V nBYPASS DDOA nc 4 39 QA V 5 ICS844S42I 38 nQA DD 6 GND REF CLK 37 56-Lead VFQFN GND 7 36 GND 8mm x 8mm x 0.925mm REF SEL 8 35 GND package body XTAL IN 9 GND 34 K Package XTAL OUT 10 33 QB nMR 11 Top View 32 nQB LOCK DT 12 31 V DDOB LEV SEL 13 30 V DDOB V 14 29 DD nc 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2016 Integrated Device Technology, Inc 1 Revision A April 28, 2016 VDD GND P NA0 NA1 NA2 NB0 NB1 NB2 SDA SCL nPLOAD GND VDD844S42I Data Sheet Block Diagram f 1 QA NA QA REF CLK f VCO 0 0 PLL P XTAL IN f f 1 REF PD OSC f QB NB QB XTAL OUT REF SEL M SDA PLL SCL Configuration Registers ADR 1:0 nPLOAD 2 LOCK DT I C Control M 9:0 NA 2:0 NB 2:0 P LEV SEL nBYPASS nMR 2016 Integrated Device Technology, Inc 2 Revision A April 28, 2016