nCLK Differential-to-0.7V HCSL Differential PCI 871002I-02 EXPRESS Jitter Attenuator DATA SHEET General Description Features The 871002I-02 is a high performance Jitter Attenuator designed for Two 0.7V HCSL differential output pairs use in PCI Express systems. In some PCI Express systems, such One differential clock input as those found in desktop PCs, the PCI Express clocks are CLK, nCLK can accept the following differential input levels: generated from a low bandwidth, high phase noise PLL frequency LVPECL, LVDS, HSTL, HCSL, SSTL synthesizer. In these systems, a jitter attenuator may be required to Input frequency range: 98MHz to 128MHz attenuate high frequency random and deterministic jitter components Output frequency range: 98MHz to 640MHz from the PLL synthesizer and from the system board. The 871002I-02 has two PLL bandwidth modes: 350kHz and 2200kHz. VCO range: 490MHz - 640MHz The 350kHz mode provides the maximum jitter attenuation, but it also Cycle-to-cycle jitter: 45ps (maximum) results in higher PLL tracking time. In this mode, the spread spectrum Two bandwidth modes allow the system designer to make jitter modulation may also be attenuated. The 2200kHz bandwidth attenuation/tracking skew design trade-offs provides the best tracking skew and will pass most spread profiles, Full 3.3V supply mode but the jitter attenuation will not be as good as the lower bandwidth modes. The 871002I-02 can be set for different modes using the -40C to 85C ambient operating temperature F SELx pins as shown in Table 3C. Available in lead-free (RoHS 6) package rd TM The 871002I-02 uses IDT 3 Generation FemtoClock PLL technology to achieve the lowest possible phase noise. The device is packaged in a small 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. PLL Bandwidth (typical) Table BW SEL 0 = PLL Bandwidth: ~350kHz (default) 1 = PLL Bandwidth: ~2200kHz Block Diagram IREF Pullup OE 2 Pullup:Pulldown F SEL 1:0 Pin Assignment Pulldown BW SEL nQ0 Q0 1 20 0 = 350kHz Output Divider Q0 2 19 VDD IREF 1 = 2200kHz 00 5 FB OUT 3 18 Q1 01 4 nQ0 nFB OUT 4 17 nQ1 10 2 (default) Pulldown CLK MR 5 16 nFB IN 11 1 Phase VCO BW SEL 6 15 FB IN Pullup nCLK 490 - 640 MHz F SEL1 GND 7 14 Detector Q1 V 8 13 DDA F SEL0 9 12 CLK nQ1 V 10 11 OE Pulldown DD FB IN Pullup nFB IN 871002I-02 20-Lead TSSOP 5 (fixed) FB OUT 6.5mm x 4.4mm x 0.925mm package body nFB OU G Package Top View Pulldown MR 871002I-02 Rev A 7/13/15 1 2015 Integrated Device Technology, Inc.871002I-02 DATA SHEET Table 1. Pin Descriptions Number Name Type Description 1, 20 nQ0, nQ0 Output Differential output pair. HCSL interface levels. A fixed precision resistor (475 ) from this pin to ground provides a reference 2 IREF Input current used for differential current-mode Qx/nQx clock outputs. 3, FB OUT, Output Differential feedback output pair. HCSL interface levels. 4 nFB OUT Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx, FB OUT) to go low and the inverted outputs (nQx, 5 MR Input Pulldown nFB OUT) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 6 BW SEL Input Pulldown PLL Bandwidth select input. 0 = 350kHz, 1 = 2200kHz. See Table 3B. 7, F SEL1, Pullup Input Frequency select pins. See Table 3C. LVCMOS/LVTTL interface levels 9 F SEL0 Pulldown 8V Power Analog supply pin. DDA 10, 19 V Power Core supply pins. DD Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are 11 OE Input Pullup in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. 12 CLK Input Pulldown Non-inverting differential clock input. 13 nCLK Input Pullup Inverting differential clock input. 14 GND Power Power supply ground. 15 FB IN Input Pulldown Non-inverting differential feedback clock input. 16 nFB IN Input Pullup Inverting differential feedback clock input. 17, 18 nQ1, Q1 Output Differential output pair. HCSL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN DIFFERENTIAL-TO-0.7V HCSL DIFFERENTIAL PCI EXPRESS JITTER 2 Rev A 7/13/15 ATTENUATOR