IREF F SEL1 CLK Differential-to-HCSL Differential ICS871004I-04 PCI EXPRESS Jitter Attenuator DATA SHEET General Description Features The ICS871004I-04 is a high performance Jitter Attenuator designed Four differential HCSL output pairs for use in PCI Express systems. In some PCI Express systems, One differential clock input such as those found in desktop PCs, the PCI Express clocks are CLK, nCLK can accept the following differential input levels: generated from a low bandwidth, high phase noise PLL frequency LVPECL, LVDS, HSTL, HCSL synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components Output frequency range: 98MHz to 640MHz from the PLL synthesizer and from the system board. The Input frequency range: 98MHz to 128MHz ICS871004I-04 has three PLL bandwidth modes: 200kHz, 700kHz and 1700kHz. The 200kHz mode provides the maximum jitter VCO range: 490MHz - 640MHz attenuation, but it also results in higher PLL tracking time. In this Cycle-to-cycle jitter: 7.5ps (typical) mode, the spread spectrum modulation may also be attenuated. The 700kHz bandwidth provides an intermediate bandwidth that can Three bandwidth modes allow the system designer to make jitter easily track tri-angular spread profiles, while providing good jitter attenuation/tracking skew design trade-offs attenuation. The 1700kHz bandwidth provides the best tracking skew Full 3.3V supply mode and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. The ICS871004I-04 can be -40C to 85C ambient operating temperature set for different modes using the F SELx pins as shown in Table 3C. Available in lead-free (RoHS 6) package RD The ICS871004I-04 uses IDTs 3 Generation FemtoClock PLL technology to achieve the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in PLL Bandwidth (typical) Table space constrained applications such as PCI Express add-in cards. BW SEL 1:0 00 = PLL Bandwidth: ~200kHz 01 = PLL Bandwidth: ~700kHz (default) 10 = PLL Bandwidth: ~1700kHz 11 = PLL BYPASS Block Diagram Pin Assignment 1 24 Q0 nQ0 IREF 2 23 nQ2 V DD Q2 3 22 Q1 Pullup OE V 4 21 DD nQ1 5 20 2 Q3 Pulldown F SEL 1:0 6 19 GND nQ3 7 18 2 MR BW SEL1 PU:PD Control BW SEL 1:0 BW SEL0 8 17 Logic Q0 V 9 16 DDA GND 15 GND F SEL0 10 nQ0 V nCLK DD 11 14 OE 12 13 M Q1 0 0 5 U (default) Phase VCO nQ1 Pulldown ICS871004I-04 X CLK 490 - 640MHz 0 1 4 Detector 24-Lead TSSOP Pullup nCLK 1 0 2 Q2 4.4mm x 7.8mm x 0.925mm 1 1 1 package body nQ2 G Package Q3 Top View 5 nQ3 Pulldown MR ICS871004AGI-04I REVISION A SEPTEMBER 5, 2012 1 2012 Integrated Device Technology, Inc.ICS871004I-04 Data Sheet PCI EXPRESS JITTER ATTENUATOR Table 1. Pin Descriptions Number Name Type Description 1, 24 nQ0, Q0 Output Differential output pair. HCSL interface levels. 2, 3 nQ2, Q2 Output Differential output pair. HCSL interface levels. 4, 11, 23 V Power Core supply pins. DD An external fixed precision resistor (475 ) from this pin to ground provides a 5 IREF Input reference current used for differential current-mode Qx, nQx clock outputs. 6, 15, 16 GND Power Power supply ground. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inverted outputs (nQx) to go high. 7 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 8 BW SEL0 Input Pullup Selects the PLL Bandwidth input. 9V Power Analog supply pin. DDA 10, F SEL0, Input Pulldown Frequency select pins.LVCMOS/LVTTL interface levels 17 F SEL1 Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are 12 OE Input Pullup in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. 13 CLK Input Pulldown Non-inverting differential clock input. 14 nCLK Input Pullup Inverting differential clock input. 18 BW SEL1 Input Pulldown Selects the PLL Bandwidth input. 19, 20 nQ3, Q3 Output Differential output pair. HCSL interface levels. 21, 22 nQ1, Q1 Output Differential output pair. HCSL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN ICS871004AGI-04I REVISION A SEPTEMBER 5, 2012 2 2012 Integrated Device Technology, Inc.