nCLK PCI Express Jitter Attenuator ICS874001I-02 DATA SHEET General Description Features The ICS874001I-02 is a high performance Jitter Attenuator designed One differential LVDS output pair for use in PCI Express systems. In some PCI Express systems, One differential clock input such as those found in desktop PCs, the PCI Express clocks are CLK, nCLK can accept the following differential input levels: generated from a low bandwidth, high phase noise PLL frequency LVPECL, LVDS, LVHSTL, HCSL, SSTL synthesizer. In these systems, a jitter attenuator may be required to Input frequency range: 98MHz to 128MHz attenuate high frequency random and deterministic jitter Output frequency range: 98MHz to 640MHz components from the PLL synthesizer and from the system board. The ICS874001I-02 has two different PLL bandwidth modes: 2MHz VCO range: 490MHz - 640MHz and 3MHz. The 2MHz mode will provide maximum jitter attenuation, Cycle-to-cycle jitter: 15ps (maximum), 3.3V but with higher PLL tracking skew and spread spectrum modulation RMS period jitter: 3ps (maximum), 3.3V from the motherboard synthesizer may be attenuated. The 3MHz bandwidth provides the best tracking skew and will pass most Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs spread profiles, but the jitter attenuation will not be as good as the lower bandwidth mode. The 874001I-02 can be set for different Full 3.3V or 2.5V operating supply modes using the F SELx pins, as shown in Table 3C. -40C to 85C ambient operating temperature RD The ICS874001I-02 uses IDTs 3 Generation FemtoClock Available in lead-free (RoHS 6) package PLL technology to achieve the lowest possible phase noise. The device is packaged in a small 20-pin TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. PLL Bandwidth Control Table BW SEL 0 = PLL Bandwidth: 2MHz (default) 1 = PLL Bandwidth: 3MHz Pin Assignment PLL SEL 1 20 nc nc 2 19 VDDO PLL SEL Control Table nc 3 18 Q nc 4 17 nQ PLL SEL MR 5 16 nc BW SEL 6 15 nc 0 = Bypass F SEL1 7 14 GND V 8 13 1 = VCO (default) DDA F SEL0 9 12 CLK V 10 11 OE DD ICS874001I-02 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View ICS874001AGI-02 REVISION A AUGUST 30, 2010 1 2010 Integrated Device Technology, Inc.ICS74001I-02 Data Sheet PCI EXPRESS JITTER ATTENUATOR Block Diagram Pullup PLL SEL Pulldown BW SEL 0 = 2MHz 1 = 3MHz 0 Output Divider Q 0 0 5 Pulldown CLK 0 1 4 nQ Pullup 1 0 2 (default) nCLK Phase VCO 1 1 1 1 Detector 490 - 640MHz Internal Feedback 5 2 Pullup/Pulldown F SEL 1:0 Pulldown MR Pullup OE ICS874001AGI-02 REVISION A AUGUST 30, 2010 2 2010 Integrated Device Technology, Inc.