874001AGI-05LF Renesas

nCLK PCI Express Jitter Attenuator ICS874001I-05 DATA SHEET General Description Features The ICS874001I-05 is a high performance Jitter Attenuator designed One differential LVDS output pair for use in PCI Express systems. In some PCI Express systems, One differential clock input such as those found in desktop PCs, the PCI Express clocks are CLK, nCLK supports the following input levels: LVPECL, LVDS, generated from a low bandwidth, high phase noise PLL frequency LVHSTL, SSTL, HCSL synthesizer. In these systems, a jitter attenuator may be required to Input frequency range: 98MHz to 128MHz attenuate high frequency random and deterministic jitter Output frequency range: 98MHz to 640MHz components from the PLL synthesizer and from the system board. The ICS874001I-05 has a bandwidth of 6MHz with <1dB peaking, VCO range: 490MHz - 640MHz easily meeting PCI Express Gen2 PLL requirements. Cycle-to-cycle jitter: 50ps (maximum) RD The ICS874001I-05 uses IDTs 3 Generation FemtoClock Full 3.3V operating supply PLL technology to achieve the lowest possible phase noise. The PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant device is packaged in a small 20-pin TSSOP package, making it -40C to 85C ambient operating temperature ideal for use in space constrained applications such as PCI Express add-in cards. Available in lead-free (RoHS 6) package Pin Assignment PLL SEL 1 20 nc nc 2 19 VDDO nc 3 18 Q nc 4 17 nQ MR 5 16 nc nc 6 15 nc F SEL1 7 14 GND V 8 13 DDA F SEL0 9 12 CLK V 10 11 OE DD ICS874001I-05 20-Lead TSSOP Block Diagram 6.5mm x 4.4mm x 0.925mm package body Pullup PLL SEL G Package Top View 0 Output Divider Q 0 0 5 Pulldown CLK 0 1 4 nQ Pullup 1 0 2 (default) VCO nCLK Phase 1 1 1 1 490 - 640MHz Detector Internal Feedback 5 Pulldown MR 2 Pullup/Pulldown F SEL 1:0 Pullup OE ICS874001AGI-05 REVISION A JANUARY 14, 2011 1 2011 Integrated Device Technology, Inc.ICS74001I-05 Data Sheet PCI EXPRESS JITTER ATTENUATOR Table 1. Pin Descriptions Number Name Type Description PLL select pin. When LOW, bypasses the PLL. When HIGH selects the PLL. 1 PLL SEL Input Pullup LVCMOS/LVTTL interface levels. See Table 3B. 2, 3, 4, 6, nc Unused No connect. 15, 16, 20 Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go LOW and the inverted output nQ to go HIGH. 5 MR Input Pulldown When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 7 F SEL1 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. Power Analog supply pin. 8V DDA 9 F SEL0 Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. Power Core supply pin. 10 V DD Output enable. When HIGH, outputs are enabled. When LOW, forces outputs 11 OE Input Pullup to a High-Impedance state. LVCMOS/LVTTL interface levels. See Table 3A. 12 CLK Input Pulldown Non-inverting differential clock input. 13 nCLK Input Pullup Inverting differential clock input. 14 GND Power Power supply ground. 17, 18 nQ, Q Output Differential output pair. LVDS interface levels. 19 V Power Output supply pin. DDO NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4pF IN Input Pullup Resistor 51 k R PULLUP R Input Pulldown Resistor 51 k PULLDOWN ICS874001AGI-05 REVISION A JANUARY 14, 2011 2 2011 Integrated Device Technology, Inc.