PRELIMINARY PCI EXPRESS/JITTER ATTENUATOR ICS874002-02 GENERAL DESCRIPTION FEATURES The ICS874002-02 is a high performance Two differential LVDS output pairs ICS Differential-to-LVDS Jitter Attenuator designed for One differential clock input HiPerClockS use in PCI Express systems. In some PCI CLK and nCLK supports the following input types: Express systems, such as those found in desktop LVPECL, LVDS, LVHSTL, SSTL, HCSL PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. Output frequency range: 98MHz - 640MHz In these systems, a jitter attenuator may be required to Input frequency range: 98MHz - 128MHz attenuate high frequency random and deterministic jitter VCO range: 490MHz - 640MHz components from the PLL synthesizer and from the system board. The ICS874002-02 has 2 PLL bandwidth modes: 2.2MHz Cycle-to-cycle jitter: 50ps (maximum) design target and 3MHz. The 2.2MHz mode will provide maximum jitter 3.3V operating supply attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may Two bandwidth modes allow the system designer to make be attenuated. The 3MHz bandwidth provides the best track- jitter attenuation/tracking skew design trade-offs ing skew and will pass most spread profiles, but the jitter 0C to 70C ambient operating temperature attenuation will not be as good as the lower bandwidth modes. Available in lead-free (RoHS 6) package The 874002-02 can be set for differential modes using the F SELx pins as shown in Table 3C. rd TM The ICS874002-02 uses IDTs 3 Generation FemtoClock PLL BANDWIDTH (TYPICAL) PLL technology to achieve the lowest possible phase noise. BW SEL The device is packaged in a 20 Lead TSSOP package, making 0 = PLL Bandwidth: 2.2MHz (default) it ideal for use in space constrained applications such as PCI 1 = PLL Bandwidth: 3MHz Express add-in cards. BLOCK DIAGRAM PIN ASSIGNMENT nQ0 Q0 1 20 Pullup OE VDDO VDDO 2 19 FB OUT Q1 3 18 2 Pullup:Pulldown nFB OUT nQ1 F SEL 1:0 4 17 MR 5 16 nFB IN FB IN BW SEL 6 15 Pulldown BW SEL F SEL1 7 14 GND 0 = 2.2MHz Output Divider VDDA 13 nCLK Q0 8 1 = 3MHz 0 0 5 F SEL0 9 12 CLK OE 0 1 4 VDD 10 11 nQ0 1 0 2 (default) Pulldown CLK 1 1 1 ICS874002-02 Phase VCO Pullup nCLK 490 - 640 MHz 20-Lead TSSOP Detector Q1 6.5mm x 4.4mm x 0.925mm package body nQ1 Pulldown FB IN G Package Pullup nFB IN Top View 5 (fixed) FB OUT nFB OUT Pulldown MR The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT / ICS PCI EXPRESS/JITTER ATTENUATOR 1 ICS874002AG-02 REV. A NOVEMBER 12, 2008ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY TABLE 1. PIN DESCRIPTIONS NeumberNeam Tnyp Descriptio 10, 20ntQ0, QO.utpu Differential output pair. LVDS interface levels 2V, 19P.ower Output supply pins DDO 3, FB OUT, Output Differential feedback output pair. LVDS interface levels. 4 nFB OUT Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx, FB OUT) to go low and the inverted 5RMtInnpu Pulldow outputs (nQx, nFB OUT) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bandwidth select input. LVCMOS/LVTTL interface levels. 6LBtW SEInnpu Pulldow See Table 3B. 71Ft SELIpnpu Pullu Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. 8VP.ower Analog supply pin DDA 90Ft SELInnpu Pulldow Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. 1V0 P.ower Core supply pin DD Output enable pin. When HIGH, the outputs are active. When LOW, the 1E1 OtIpnpu Pullu outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. 1K2 CtL InnpuP.ulldow Non-inverting differential clock input 1K3 ntCL IpnpuP.ullu Inverting differential clock input 1D4 GrNP.owe Power supply ground 1N5 FtB IInnpuP.ulldow Non-inverting differential feedback input 1N6ntFB IIpnpuP.ullu Inverting differential feedback input 117, 18ntQ1, QO.utpu Differential output pair. LVDS interface levels NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS SrymbolPsaramete Tmest Condition MlinimuTmypicaMsaximu Unit C Input Capacitance 4Fp IN R Input Pullup Resistor 5k1 PULLUP R Input Pulldown Resistor 5k1 PULLDOWN TABLE 3A. OUTPUT ENABLE FUNCTION TABLE TABLE 3B. PLL BANDWIDTH CONTROL TABLE Isnput Output Input O EQT 0:1 / nQ 0:1 FB OUT/nFB OU BW SEL PLL Bandwidth 0)2.2MHz (default 0eHdigh Impedanc Enable 1dEdnable Enable 1z3MH TABLE 3C. F SELX FUNCTION TABLE Inputs Input Frequency Output Frequency (MHz)F0 SEL1Fr SEL Divide (MHz) 1000 0 5 100 1000 1 4 125 1100 0 2 250 (default) 1100 1 1 500 IDT / ICS PCI EXPRESS/JITTER ATTENUATOR 2 ICS874002AG-02 REV. A NOVEMBER 12, 2008