nCLK PCI EXPRESS Jitter Attenuator ICS874003-02 DATA SHEET General Description Features The ICS874003-02 is a high performance Differential-to- LVDS Jitter Three differential LVDS output pairs Attenuator designed for use in PCI Express systems. In some PCI One differential clock input Express systems, such as those found in desktop PCs, the PCI CLK, nCLK supports the following input levels: LVPECL, LVDS, Express clocks are generated from a low bandwidth, high phase LVHSTL, HCSL, SSTL noise PLL frequency synthesizer. In these systems, a jitter Input frequency range: 98MHz to 128MHz attenuator may be required to attenuate high frequency random and Output frequency range: 98MHz to 320MHz deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003-02 has a bandwidth of 400kHz VCO range: 490MHz - 640MHz which is designed to provide good jitter attenuation. Cycle-to-cycle jitter: 35ps (maximum) RD For PCI Express Spread Spectrum Clocking support use the The ICS874003-02 uses IDTs 3 Generation Femtoclock PLL ICS874003-05 technology to achieve the lowest possible phase noise. The device is Full 3.3V supply mode packaged in a 20 lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment F SEL 2:0 Function Table QA1 1 20 nQA1 Inputs Outputs V 2 19 VDDO DDO F SEL2 F SEL1 F SEL0 QA 0:1 , nQA 0:1 QB0, nQB0 QA0 3 18 QB0 nQA0 4 17 nQB0 00 0 2 2 MR 5 16 F SEL2 F SEL0 6 15 OEB 10 0 5 2 nc 7 14 GND V 8 13 DDA 01 0 4 2 F SEL1 9 12 CLK V 10 11 OEA 11 0 2 4 DD ICS874003-02 00 1 2 5 20-Lead TSSOP 10 1 5 4 6.5mm x 4.4mm x 0.925mm package body 01 1 4 5 G Package Top View 11 1 4 4 ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 1 2010 Integrated Device Technology, Inc.ICS874003-02 Data Sheet PCI EXPRESS JITTER ATTENUATOR Block Diagram Pullup OEA 3 Pulldown F SEL2:0 QA0 5 4 nQA0 2 (default) QA1 Pulldown CLK Phase VCO nQA1 Pullup 490 - 640MHz nCLK Detector 3 QB0 5 4 2 (default) nQB0 M = 5 (fixed) Pulldown MR ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 2 2010 Integrated Device Technology, Inc. Pullup OEB