nCLK PCI EXPRESS JITTER ATTENUATOR ICS874003I-02 GENERAL DESCRIPTION FEATURES The ICS874003I-02 is a high performance Dif-ferential-to-LVDS Three Differential LVDS output pairs Jitter Attenuator designed for use in PCI Express systems. In One Differential clock input some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low CLK and nCLK supports the following input types: bandwidth, high phase noise PLL frequency synthesizer. In these LVPECL, LVDS, LVHSTL, SSTL, HCSL systems, a jitter attenuator may be required to attenuate high Output frequency range: 98MHz - 320MHz frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003I- Input frequency range: 98MHz - 128MHz 02 has a bandwidth of 400kHz. The 400kHz provides an VCO range: 490MHz - 640MHz intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. Cycle-to-cycle jitter: 35ps (maximum) Supports PCI-Express Spread-Spectrum Clocking rd TM The ICS874003I-02 uses IDTs 3 Generation FemtoClock The 400kHz bandwidth mode allows the system designer to PLL technology to achive the lowest possible phase noise. make jitter attenuation/tracking skew design trade-offs The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI 3.3V operating supply Express add-in cards. -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging F SEL 2:0 FUNCTION TABLE Isnputs Output F1 SEL2F0 SELF1 SELQ0A0, nQA0:QA1, nQA QB0, nQB 00 0 22 10 0 25 01 0 24 11 0 42 00 1 52 10 1 45 01 1 54 BLOCK DIAGRAM 11 1 44 Pullup OEA 3 PIN ASSIGNMENT Pulldown F SEL2:0 QA0 QA1 1 20 nQA1 5 V 2 19 VDDO DDO 4 QA0 3 18 QB0 nQA0 2 (default) nQA0 4 17 nQB0 MR 5 16 F SEL2 QA1 F SEL0 6 15 OEB Pulldown CLK nc 7 14 GND Phase VCO V 8 13 DDA nQA1 Pullup nCLK 490 - 640MHz F SEL1 9 12 CLK Detector 3 10 11 V OEA DD QB0 ICS874003I-02 5 4 20-Lead TSSOP 2 (default) nQB0 M = 5 (fixed) 6.5mm x 4.4mm x 0.92mm package body G Package Pulldown MR Top View IDT / ICS PCI EXPRESS JITTER ATTENUATOR 1 ICS874003AGI-02 REV A MAY 1, 2013 Pullup OEBICS874003I-02 PCI EXPRESS JITTER ATTENUATOR TABLE 1. PIN DESCRIPTIONS NeumberNeam Tnyp Descriptio 11, 20QtA1, nQAO.utpu Differential output pair. LVDS interface levels 2V, 19 P.ower Output supply pins DDO 30, 4QtA0, nQAO.utpu Differential output pair. LVDS interface levels Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inverted outputs 5RMtInnpu Pulldow (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 6, F SEL0, Frequency select pin for QAx/nQAx and QBx0/nQB0 outputs. 9, F SEL1,Innput Pulldow LVCMOS/LVTTL interface levels. 16 F SEL2 7cndU.nuse No connect 8VP.ower Analog supply pin DDA 1V0 P.ower Core supply pin DD Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are 1A1 OtE Ipnpu Pullu active. When LOW, the QAx/nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. 1K2 CtL InnpuP.ulldow Non-inverting differential clock input 1K3 ntCL IpnpuP.ullu Inverting differential clock input 1D4 GrNP.owe Power supply ground Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are 1B5 OtE Ipnpu Pullu active. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. 107, 18ntQB0, QBO.utpu Differential output pair. LVDS interface levels NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS SrymbolPsaramete Tmest Condition MlinimuTmypicaMsaximu Unit C Input Capacitance 4Fp IN R Input Pullup Resistor 5k1 PULLUP R Input Pulldown Resistor 5k1 PULLDOWN TABLE 3. OUTPUT ENABLE FUNCTION TABLE Isnputs Output OBEAO1EQ0A0/nQA0, QA1/nQA QB0/nQB 00 HZiZ Hi 11Ednabled Enable IDT / ICS PCI EXPRESS JITTER ATTENUATOR 2 ICS874003AGI-02 REV A MAY 1, 2013