PCI Express 874003 Jitter Attenuator DATA SHEET GENERAL DESCRIPTION FEATURES The 874003 is a high performance Differential-to-LVDS Jitter Three Differential LVDS output pairs Attenuator designed for use in PCI Express systems. In some One Differential clock input PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high CLK and nCLK supports the following input types: phase noise PLL frequency synthesizer. In these systems, a jitter LVPECL, LVDS, LVHSTL, SSTL, HCSL attenuator may be required to attenuate high frequency random Output frequency range: 98MHz - 160MHz and deterministic jitter components from the PLL synthesizer and from the system board. The 874003 has 3 PLL bandwidth Input frequency range: 98MHz - 128MHz modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will VCO range: 490MHz - 640MHz provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard Cycle-to-cycle jitter: 35ps (maximum) synthesizer may be attenuated. The 400kHz provides an 3.3V operating supply intermediate bandwidth that can easily track triangular spread pro les, while providing good jitter attenuation. The 800kHz Three bandwidth modes allow the system designer to make bandwidth provides the best tracking skew and will pass most jitter attenuation/tracking skew design trade-offs spread pro les, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes 0C to 70C ambient operating temperature have x20 multipliers while others have than x25 multipliers, the Available in lead-free RoHS compliant package 874003 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the FSEL pins. rd The 874003 uses IDTs 3 Generation FemtoClock PLL technology to achive the lowest possible phase noise. PLL BANDWIDTH The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI BW SEL Express add-in cards. 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~400kHz (default) 1 = PLL Bandwidth: ~800kHz BLOCK DIAGRAM Pullup OEA PIN ASSIGNMENT F SELA Pulldown QA0 BW SEL Float F SELA 0 = ~200kHz 0 5 (default) Float = ~400kHz nQA0 1 4 1 = ~800kHz QA1 CLK Pulldown Phase VCO nQA1 nCLK Pullup 490 - 640MHz Detector 874003 QB0 20-Lead TSSOP F SELB 0 5 (default) 6.5mm x 4.4mm x 0.92mm 1 4 nQB0 M = 5 (fixed) package body G Package Top View F SELB Pulldown Pulldown MR OEB Pullup 874003 REVISION A 7/16/15 1 2015 Integrated Device Technology, Inc.874003 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 20 QA1, nQA1 Output Differential output pair. LVDS interface levels. 2, 19 V Power Output supply pins. DDO 3, 4 QA0, nQA0 Output Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQXx) to go low and the inverted outputs 5 MR Input Pulldown (QXx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup/ 6 BW SEL Input PLL Bandwidth input. See Table 3B. Pulldown 7 nc Unused No connect. 8V Power Analog supply pin. DDA Frequency select pin for QAx/nQAx outputs. 9 F SELA Input Pulldown LVCMOS/LVTTL interface levels. 10 V Power Core supply pin. DD Output enable pin for QAx/nQAx pins. When HIGH, the QAx/nQAx out- 11 OEA Input Pullup puts are active. When LOW, the QAx/nQAx outputs are in a high imped- ance state. LVCMOS/LVTTL interface levels. 12 CLK Input Pulldown Non-inverting differential clock input. 13 nCLK Input Pullup Inverting differential clock input. 14 GND Power Power supply ground. Output enable pin for QB0 pins. When HIGH, the QB0/nQB0 outputs are 15 OEB Input Pullup active. When LOW, the QB0/nQB0 outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Frequency select pin for QB0/nQB0 outputs. 16 F SELB Input Pulldown LVCMOS/LVTTL interface levels. 17, 18 nQB0, QB0 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN TABLE 3A. OUTPUT ENABLE FUNCTION TABLE TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL Inputs Outputs Inputs PLL Band- width OEA OEB QA0:1, nQA0:1 QB0/nQB0 PLL BW 0 0 HiZ HiZ 0 ~200kHz 1 1 Enabled Enabled 1 ~800kHz Float ~400kHz PCI EXPRESS 2 REVISION A 7/16/15 JITTER ATTENUATOR