nCLK PCI Express Jitter Attenuator ICS874003-05 DATASHEET General Description Features The ICS874003-05 is a high performance Differential-to-LVDS Jitter Three differential LVDS output pairs Attenuator designed for use in PCI Express systems. In some PCI One differential clock input Express systems, such as those found in desktop PCs, the PCI CLK/nCLK can accept the following differential input levels: Express clocks are generated from a low bandwidth, high phase LVPECL, LVDS, LVHSTL, HCSL, SSTL noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and Input frequency range: 98MHz to 128MHz deterministic jitter components from the PLL synthesizer and from Output frequency range: 98MHz to 320MHz the system board. The ICS874003-05 has a bandwidth of 6.2MHz with <1dB peaking, easily meeting PCI Express Gen2 PLL VCO range: 490MHz - 640MHz requirements. Supports PCI-Express Spread-Spectrum Clocking rd The ICS874003-05 uses IDTs 3 Generation FemtoClock PLL High PLL bandwidth allows for better input tracking technology to achieve the lowest possible phase noise. The device is PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant packaged in a 20-Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. 0C to 70C ambient operating temperature Full 3.3V operating supply Available in lead-free (RoHS 6) packages F SEL 2:0 Function Table Pin Assignment Inputs Outputs QA1 1 20 nQA1 V 2 19 VDDO DDO QA 0:1 , QA0 3 18 QB0 F SEL2 F SEL1 F SEL0 nQA 0:1 QB0, nQB0 nQA0 4 17 nQB0 MR 5 16 F SEL2 0 0 0 2 2 F SEL0 6 15 OEB (default) (default) (default) nc 7 14 GND V 8 13 DDA 100 5 2 F SEL1 9 12 CLK V 10 11 OEA DD 010 4 2 110 2 4 ICS874003-05 001 2 5 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body 101 5 4 G Package 011 4 5 Top View 111 4 4 ICS874003BG-05 REVISION B MARCH 21, 2014 1 2014 Integrated Device Technology, Inc.ICS874003-05 Data Sheet PCI EXPRESS JITTER ATTENUATOR Block Diagram Pullup OEA 3 Pulldown F SEL2:0 QA0 5 4 nQA0 2 (default) QA1 Pulldown CLK Phase VCO nQA1 Pullup 490 - 640MHz nCLK Detector 3 QB0 5 4 2 (default) nQB0 M = 5 (fixed) Pulldown MR ICS874003BG-05 REVISION B MARCH 21, 2014 2 2014 Integrated Device Technology, Inc. Pullup OEB