PCI Express Jitter Attenuator 874005-04 Data Sheet GENERAL DESCRIPTION FEATURES The 874005-04 is a high performance Differential-to-LVDS Jitter Five differential LVDS output pairs Attenuator designed for use in PCI Express systems. In some PCI One differential clock input Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise Supports 100MHz, 125MHz, and 250MHz Serdes reference PLL frequency synthesizer. In these systems, a jitter attenuator may clocks be required to attenuate high frequency random and deterministic CLK and nCLK supports the following input types: jitter components from the PLL synthesizer and from the system LVPECL, LVDS, LVHSTL, SSTL, HCSL board. The 874005-04 has 2 PLL bandwidth modes: 300kHz and 2MHz. The 300kHz mode will provide maximum jitter attenuation, Output frequency range: 98MHz - 320MHz but higher PLL tracking skew and spread spectrum modulation Input frequency range: 98MHz - 128MHz from the motherboard synthesizer may be attenuated. The 2MHz bandwidth provides the best tracking skew and will pass most PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant spread pro les. The 874005-04 supports Serdes reference clock RMS phase jitter 100MHz (1.875MHz 20MHz): frequencies of 100MHz, 125MHz and 250MHz. 0.88ps (typical) rd TM The 874005-04 uses IDTs 3 Generation FemtoClock PLL VCO range: 490MHz - 640MHz technology to achive the lowest possible phase noise. The device is Cycle-to-cycle jitter: 35ps (maximum) QA = QB = 4 packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. 3.3V operating supply Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package PLL BANDWIDTH BW SEL 0 = PLL Bandwidth: ~300kHz (default) 1 = PLL Bandwidth: ~2MHz BLOCK DIAGRAM Pullup OEA Pulldown F SELA BW SEL Pulldown QA0 PIN ASSIGNMENT F SELA 0 = ~300kHz 0 5 (default) 1 = ~2MHz nQA0 1 4 nQB2 QB2 1 24 nQA1 2 23 VDDO QA1 Pulldown CLK QA1 QB1 3 22 Phase VCO VDDO 4 nQB1 21 nQA1 Pullup nCLK 490 - 640MHz Detector QA0 5 20 QB0 nQA0 6 19 nQB0 QB0 F SELB MR 7 18 F SELB 0 2 (default) BW SEL 8 OEB 17 nQB0 1 4 9 VDDA 16 GND M = 5 (fixed) QB1 10 15 F SELA GND 11 14 VDD nCLK nQB1 13 12 OEA CLK QB2 874005-04 nQB2 24-Lead TSSOP F SELB Pulldown 4.40mm x 7.8mm x 0.925mm package body MR Pulldown G Package OEB Pullup Top View 2016 Integrated Device Technology, Inc 1 January 26, 2016874005-04 Data Sheet TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 24 nQB2, QB2 Output Differential output pair. LVDS interface levels. 2, 3 nQA1, QA1 Output Differential output pair. LVDS interface levels. 4, 23 V Power Output supply pins. DDO 5, 6 QA0, nQA0 Output Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inverted outputs (nQx) to 7 MR Input Pulldown go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 8 BW SEL Input Pulldown PLL bandwidth input. See Table 3B. LVCMOS/LVTTL interface levels. 9V Power Analog supply pin. DDA Frequency select pin for QAx/nQAx outputs. See Table 3C. LVCMOS/LVTTL 10 F SELA Input Pulldown interface levels. 11 V Power Core supply pin. DD Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are 12 OEA Input Pullup active. When LOW, the QAx/nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. 13 CLK Input Pulldown Non-inverting differential clock input. 14 nCLK Input Pullup Inverting differential clock input. 15, 16 GND Power Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are 17 OEB Input Pullup active. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. Frequency select pin for QBx/nQBx outputs. See Table 3C. LVCMOS/LVTTL 18 F SELB Input Pulldown interface levels. 19, 20 nQB0, QB0 Output Differential output pair. LVDS interface levels. 21, 22 nQB1, QB1 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc 2 January 26, 2016