PCI Express Jitter Attenuator 874005 DATA SHEET GENERAL DESCRIPTION FEATURES The 874005 is a high performance Differential-to-LVDS Jitter Five differential LVDS output pairs Attenuator designed for use in PCI Express systems. In some One differential clock input PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high CLK and nCLK supports the following input types: phase noise PLL frequency synthesizer. In these systems, a jitter LVPECL, LVDS, LVHSTL, SSTL, HCSL attenuator may be required to attenuate high frequency random Output frequency range: 98MHz - 160MHz and deterministic jitter components from the PLL synthesizer and from the system board. The 874005 has 3 PLL bandwidth Input frequency range: 98MHz - 128MHz modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will VCO range: 490MHz - 640MHz provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard Cycle-to-cycle jitter: 30ps (maximum) synthesizer may be attenuated. The 400kHz provides an 3.3V operating supply intermediate bandwidth that can easily track triangular spread pro les, while providing good jitter attenuation. The 800kHz 3 bandwidth modes allow the system designer to make bandwidth provides the best tracking skew and will pass most jitter attenuation/tracking skew design trade-offs spread pro les, but the jitter attenuation will not be as good 0C to 70C ambient operating temperature as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have than x25 multipliers, the Available in lead-free RoHS compliant package 874005 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F SEL pins. rd The 874005 uses IDTs 3 Generation FemtoClock PLL BANDWIDTH PLL technology to achive the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI BW SEL Express add-in cards. 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~400kHz (Default) 1 = PLL Bandwidth: ~800kHz PIN ASSIGNMENT BLOCK DIAGRAM nQB2 1 24 QB2 nQA1 23 VDDO 2 QA1 3 22 QB1 VDDO nQB1 4 21 20 QA0 5 QB0 6 19 nQA0 nQB0 MR 7 18 F SELB BW SEL 8 17 OEB VDDA 9 16 GND 10 15 F SELA GND 14 11 VDD nCLK 12 13 OEA CLK 874005 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View 874005 REVISION B 7/20/15 1 2015 Integrated Device Technology, Inc.874005 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 24 nQB2, QB2 Output Differential output pair. LVDS interface levels. 2, 3 nQA1, QA1 Output Differential output pair. LVDS interface levels. 4, 23 V Power Output supply pins. DDO 5, 6 QA0, nQA0 Output Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inverted outputs 7 MR Input Pulldown (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup/ 8 BW SEL Input PLL Bandwidth input. See Table 3B. Pulldown 9V Power Analog supply pin. DDA Frequency select pin for QAx,nQAx outputs. 10 F SELA Input Pulldown LVCMOS/LVTTL interface levels. 11 V Power Core supply pin. DD Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are 12 OEA Input Pullup active. When LOW, the QAx,nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. 13 CLK Input Pulldown Non-inverting differential clock input. 14 nCLK Input Pullup Inverting differential clock input. 15, 16 GND Power Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are 17 OEB Input Pullup active. When LOW, the QBx,nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Frequency select pin for QBx,nQBx outputs. 18 F SELB Input Pulldown LVCMOS/LVTTL interface levels. 19, 20 nQB0, QB0 Output Differential output pair. LVDS interface levels. 21, 22 nQB1, QB1 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 4 pF IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN TABLE 3A. OUTPUT ENABLE FUNCTION TABLE TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL Inputs Outputs Inputs PLL Band- OEA/OEB QAx/nQAx QBx/nQBx width PLL BW 0 HiZ HiZ 0 ~200kHz 1 Enabled Enabled 1 ~800kHz Float ~400kHz PCI Express Jitter Attenuator 2 REVISION B 7/20/15