nQA0 OEB CLK Differential-to-LVDS/0.7V Differential PCI 8741004 Express Jitter Attenuator DATA SHEET General Description Features The 8741004 is a high performance Differential-to-LVDS/0.7V Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Differential Jitter Attenuator designed for use in PCI Express Bank B has two 0.7V differential output pairs systems. In some PCI Express systems, such as those found in One differential clock input pair desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these CLK, CLK pair can accept the following differential systems, a jitter attenuator may be required to attenuate high input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL frequency random and deterministic jitter components from the PLL Output frequency range: 98MHz - 160MHz synthesizer and from the system board. The 8741004 has 3 PLL Input frequency range: 98MHz - 128MHz bandwidth modes: 200kHz, 600kHz and 2MHz. The 200kHz mode VCO range: 490MHz - 640MHz will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard Cycle-to-cycle jitter: 35ps (maximum) synthesizer may be attenuated. The 600kHz provides an Full 3.3V operating supply intermediate bandwidth that can easily track triangular spread Three bandwidth modes allow the system designer to make jitter profiles, while providing good jitter attenuation. The 2MHz bandwidth attenuation/tracking skew design trade-offs provides the best tracking skew and will pass most spread profiles, 0C to 70C ambient operating temperature but the jitter attenuation will not be as good as the lower bandwidth Available in lead-free (RoHS 6) package modes. Because some 2.5Gb serdes have x20 multipliers while others have x25 multipliers, the 8741004 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F SEL pins. rd Generation FemtoClock The 8741004 uses IDTs 3 PLL technology to achieve the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express Pin Assignment add-in cards. nQB1 nQA1 1 24 QA1 2 23 QB1 PLL Bandwidth V V DDO 3 22 DDO QA0 4 21 QB0 BW SEL 5 20 nQB0 0 = PLL Bandwidth: ~200kHz MR 6 19 IREF Float = PLL Bandwidth: ~600kHz (default) F SELB BW SEL 7 18 nc 8 17 1 = PLL Bandwidth: ~2MHz V GND DDA 9 16 GND F SELA 10 15 V DD 11 14 nCLK OEA 12 13 8741004 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Top View 8741004 Rev A 7/20/15 1 2015 Integrated Device Technology, Inc.8741004 DATA SHEET Block Diagram Pullup OEA Pulldown F SELA QA0 Float BW SEL F SELA 0 = ~200kHz 0 5 (default) Float = ~400kHz nQA0 1 = ~800kHz 1 4 QA1 Pulldown CLK Phase VCO nQA1 Pullup 490 - 640 MHz nCLK Detector QB0 F SELB 0 5 (default) nQB0 1 4 M = 5 (fixed) QB1 nQB1 Pulldown F SELB Pulldown MR IREF Pullup OEB DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER 2 Rev A 7/20/15 ATTENUATOR