89HPES12N3A 12-lane 3-Port Data Sheet PCI Express Switch Flexible Architecture with Numerous Configuration Options Device Overview Automatic per port link width negotiation to x4, x2 or x1 The 89HPES12N3A is a member of the IDT PRECISE family of Automatic lane reversal on all ports PCI Express switching solutions. The PES12N3A is a 12-lane, 3-port Automatic polarity inversion on all lanes peripheral chip that performs PCI Express packet switching with a Ability to load device configuration from serial EEPROM feature set optimized for high performance applications such as servers, Legacy Support storage, and communications/networking. It provides connectivity and switching functions between a PCI Express upstream port and two PCI compatible INTx emulation downstream ports and supports switching between downstream ports. Bus locking Highly Integrated Solution Features Requires no external components High Performance PCI Express Switch Incorporates on-chip internal memory for packet buffering and queueing Twelve 2.5Gbps PCI Express lanes Integrates twelve 2.5 Gbps embedded SerDes with 8B/10B Three switch ports encoder/decoder (no separate transceivers needed) Upstream port configurable up to x4 Reliability, Availability, and Serviceability (RAS) Features Downstream ports configurable up to x4 Supports ECRC and Advanced Error Reporting Low-latency cut-through switch architecture Internal end-to-end parity protection on all TLPs ensures data Support for Max Payload Sizes up to 2048 bytes integrity even in systems that do not implement end-to-end One virtual channel CRC (ECRC) Eight traffic classes Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O PCI Express Base Specification Revision 1.1 compliant Compatible with Hot-Plug I/O expanders used on PC and server motherboards Block Diagram 3-Port Switch Core Port Scheduler Route Table Scheduler Frame Buffer Arbitration Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Multiplexer/Demultiplexer Multiplexer/Demultiplexer Multiplexer/Demultiplexer Phy Phy Phy Phy Phy Phy Phy Phy Phy Phy Phy Phy Logical Logical Logical Logical Logical Logical Logical Logical Logical Logical Logical Logical Layer Layer Layer Layer Layer Layer Layer Layer Layer Layer Layer Layer SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes 12 PCI Express Lanes One x4 Upstream Port and Two x4 Downstream Ports Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 31 April 9, 2010 DSC 6922IDT 89HPES12N3A Data Sheet Power Management Slave Master Utilizes advanced low-power design techniques to achieve low Bit SMBus SMBus typical power consumption Address Address Supports PCI Power Management Interface specification 4 0 MSMBADDR 4 (PCI-PM 1.1) Supports device power management states: D0, D3 and 5 SSMBADDR 5 1 hot D3 cold 61 0 Unused SerDes are disabled Testability and Debug Features 71 1 Ability to read and write any internal register via the SMBus Table 1 Master and Slave SMBus Address Assignment Eight General Purpose Input/Output Pins Each pin may be individually configured as an input or output As shown in Figure 2, the master and slave SMBuses may be used Each pin may be individually configured as an interrupt input in a unified or split configuration. In the unified configuration, shown in Some pins have selectable alternate functions Figure 2(a), the master and slave SMBuses are tied together and the Packaged in 19x19mm 324-ball BGA with 1mm ball spacing PES12N3A acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has Product Description access to PES12N3A registers supports SMBus arbitration. In some Utilizing standard PCI Express interconnect, the PES12N3A systems, this SMBus master interface may be implemented using provides the most efficient I/O connectivity solution for applications general purpose I/O pins on a processor or micro controller, and may requiring high throughput, low latency, and simple board layout with a not support SMBus arbitration. To support these systems, the minimum number of board layers. It provides connectivity for up to 3 PES12N3A may be configured to operate in a split configuration as ports across 12 integrated serial lanes. Each lane provides 2.5 Gbps of shown in Figure 2(b). bandwidth in both directions and is fully compliant with PCI Express In the split configuration, the master and slave SMBuses operate as Base specification revision 1.1. two independent buses and thus multi-master arbitration is never required. The PES12N3A supports reading and writing of the serial SMBus Interface EEPROM on the master SMBus via the slave SMBus, allowing in The PES12N3A contains two SMBus interfaces. The slave interface system programming of the serial EEPROM. provides full access to the configuration registers in the PES12N3A, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configura- tion register values of the PES12N3A to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be config- ured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1. Slave Master Bit SMBus SMBus Address Address 1 SSMBADDR 1 MSMBADDR 1 2 SSMBADDR 2 MSMBADDR 2 3 SSMBADDR 3 MSMBADDR 3 Table 1 Master and Slave SMBus Address Assignment 2 of 31 April 9, 2010