89HPES12NT3 12-lane 3-Port Non-Transparent Data Sheet PCI Express Switch Flexible Architecture with Numerous Configuration Options Device Overview Port arbitration schemes utilizing round robin The 89HPES12NT3 is a member of the IDT PRECISE family of Supports automatic per port link width negotiation (x4, x2, or PCI Express switching solutions offering the next-generation I/O inter- x1) connect standard. The PES12NT3 is a 12-lane, 3-port peripheral chip Static lane reversal on all ports that performs PCI Express Base switching with a feature set optimized Automatic polarity inversion on all lanes for high performance applications such as servers, storage, and commu- Supports locked transactions, allowing use with legacy soft- ware nications/networking. It provides high-performance I/O connectivity and Ability to load device configuration from serial EEPROM switching functions between a PCIe upstream port, a transparent Ability to control device via SMBus downstream port, and a non-transparent downstream port. Non-Transparent Port With non-transparent bridging (NTB) functionality, the PES12NT3 Crosslink support on NTB port can be used standalone or as a chipset with IDT PCIe System Intercon- Four mapping windows supported nect Switches in multi-host and intelligent I/O applications such as Each may be configured as a 32-bit memory or I/O window communications, storage, and blade servers where inter-domain May be paired to form a 64-bit memory window communication is required. Interprocessor communication Thirty-two inbound and outbound doorbells Four inbound and outbound message registers Features Two shared scratchpad registers High Performance PCI Express Switch Allows up to sixteen masters to communicate through the non- Twelve PCI Express lanes (2.5Gbps), three switch ports transparent port Delivers 48 Gbps (6 GBps) of aggregate switching capacity No limit on the number of supported outstanding transactions Low latency cut-through switch architecture through the non-transparent bridge Support for Max Payload size up to 2048 bytes Completely symmetric non-transparent bridge operation Supports one virtual channel and eight traffic classes allows similar/same configuration software to be run PCI Express Base specification Revision 1.0a compliant Supports direct connection to a transparent or non-transparent port of another switch Block Diagram 3-Port Switch Core Port Frame Buffer Route Table Scheduler Arbitration Transaction Layer Transaction Layer Transaction Layer Non- Transparent Bridge Data Link Layer Data Link Layer Data Link Layer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Phy Phy Phy Phy Phy Phy Phy Phy Phy Logical Logical Logical Logical Logical Logical Logical Logical Logical Layer Layer Layer Layer Layer Layer Layer Layer Layer ..... SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes SerDes 12 PCI Express Lanes x4 Upstream Port and Two x4 Downstream Ports Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.Inc. 1 of 29 February 19, 2009 DSC 6929IDT 89HPES12NT3 Data Sheet Highly Integrated Solution bandwidth allocation and/or latency for critical traffic classes in applica- Requires no external components tions such as high throughput 10 GbE I/Os, SATA controllers, and Fibre Incorporates on-chip internal memory for packet buffering and Channel HBAs. queueing Integrates twelve 2.5 Gbps embedded full duplex SerDes, Switch Configuration 8B/10B encoder/decoder (no separate transceivers needed) The PES12NT3 is a three port switch that contains 12 PCI Express Reliability, Availability, and Serviceability (RAS) Features lanes. Each of the three ports is statically allocated 4 lanes with ports Upstream port can be dynamically swapped with non-trans- labeled as A, B and C. Port A is the upstream port, port B is the trans- parent downstream port to support failover applications parent downstream port, and port C is the non-transparent downstream Internal end-to-end parity protection on all TLPs ensures data port. integrity even in systems that do not implement end-to-end CRC (ECRC) During link training, link width is automatically negotiated. Each Supports ECRC pass-through in transparent and non-trans- PES12NT3 port is capable of independently negotiating to a x4, x2 or x1 parent ports width. Thus, the PES12NT3 may be used in virtually any three port Supports Hot-Swap switch configuration (e.g., x4, x4, x4 , x4, x2, x2 , x4, x2, x1 , etc.). Power Management The PES12NT3 supports static lane reversal. For example, lane Supports PCI Power Management Interface specification, reversal for upstream port A may be configured by asserting the PCI Revision 1.1 (PCI-PM) Express Port A Lane Reverse (PEALREV) input signal or through serial Unused SerDes are disabled EEPROM or SMBus initialization. Lane reversal for ports B and C may Testability and Debug Features be enabled via a configuration space register, serial EEPROM, or the Built in SerDes Pseudo-Random Bit Stream (PRBS) generator SMBus. Ability to read and write any internal register via the SMBus Ability to bypass link training and force any link into any mode Provides statistics and performance counters Two SMBus Interfaces Slave interface provides full access to all software-visible registers by an external SMBus master Master interface provides connection for an optional serial EEPROM used for initialization Master and slave interfaces may be tied together so the switch can act as both master and slave Eight General Purpose Input/Output pins Packaged in 19x19mm 324-ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES12NT3 provides the most efficient high-performance I/O connectivity solution for applica- tions requiring high throughput, low latency, and simple board layout with a minimum number of board layers. With support for non-trans- parent bridging, the PES12NT3, as a standalone switch or as a chipset with IDT PCIe System Interconnect Switches, enables multi-host and intelligent I/O applications requiring inter-domain communication. The PES12NT3 provides 48 Gbps (6 GBps) of aggregated, full-duplex switching capacity through 12 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specifica- tion 1.0a. The PES12NT3 is based on a flexible and efficient layered architec- ture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.0a. The PES12NT3 can operate either as a store and forward or cut-through switch depending on the packet size and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management. This includes round robin port arbitration, guaranteeing 2 of 29 February 19, 2009