8A34001 Synchronization Management Unit Datasheet 12 Differential / 24 LVCMOS outputs Overview Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS) The 8A34001 Synchronization Management Unit (SMU) provides Jitter below 150fs RMS (10kHz to 20MHz) tools to manage timing references, clock sources, and timing LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL paths for IEEE 1588 and Synchronous Ethernet (SyncE) based output modes supported clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators Differential output swing is selectable: 400mV / 650mV / 800mV / 910mV (DCO), or Digital Phase Lock Loops (DPLL). Independent output voltages of 3.3V, 2.5V, or 1.8V Optional clock recovery filter/servo software is available under LVCMOS additionally supports 1.5V or 1.2V license from Renesas for use with the 8A34001. The filter/servo software is designed to suppress the effects of Packet Delay The clock phase of each output is individually programmable in 1ns to 2ns steps with a total range of 180 Variation (PDV) on packet based timing signals it can be used with protocol stacks for IEEE 1588 or other packet-based timing 8 differential / 16 single-ended clock inputs protocols. Supports frequencies from 0.5Hz to 1GHz Any input can be mapped to any or all of the timing channels Typical Applications Redundant inputs frequency independent of each other Any input can be designated as external frame/sync pulse of Core and access IP switches/routers PPES (pulse per even second), 1PPS (Pulse per Second), Synchronous Ethernet equipment 5PPS, 10PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz Telecom Boundary Clocks (T-BCs) and Telecom Time Slave associated with a selectable reference clock input Clocks (T-TSCs) according to ITU-T G.8273.2 Per-input programmable phase offset of up to 1.638 s in 10Gb, 40Gb, and 100Gb Ethernet interfaces 1ps steps Central Office Timing Source and Distribution Reference monitors qualify/disqualify references depending on Wireless infrastructure for 4.5G and 5G network equipment LOS, activity, frequency monitoring, and/or LOS input pins Loss of Signal (LOS) input pins (via GPIOs) can be assigned to any input clock reference Features Automatic reference selection state machines select the active Eight independent timing channels reference for each DPLL based on the reference monitors, Each can act as a frequency synthesizer, jitter attenuator, priority tables, revertive/non-revertive, and other Digitally Controlled Oscillator (DCO) or Digital Phase Lock programmable settings Loop (DPLL) System APLL operates from fundamental-mode crystal: 25MHz DPLLs generate telecom compliant clocks to 54MHz or from a crystal oscillator Compliant with ITU-T G.8262 for Synchronous Ethernet System DPLL accepts an XO, TCXO, or OCXO operating at virtually any frequency from 1MHz to 150MHz Compliant with legacy SONET/SDH and PDH requirements DPLLs can be configured as DCOs to synthesize Precision Time Protocol (PTP) / IEEE 1588 clocks DPLL Digital Loop Filters (DLFs) are programmable with cut off frequencies from 12Hz to 22kHz DCOs generate PTP based clocks with frequency resolution -16 less than 1.11 10 DPLL/DCO channels share frequency information using the Combo Bus to simplify compliance with ITU-T G.8273.2 DPLL Phase detectors can be used as Time-to-Digital Converters (TDC) with precision below 1ps Switching between DPLL and DCO modes is hitless and 2 dynamic Supports 1MHz I C or 50MHz SPI serial processor ports Can configure itself automatically after reset via: Automatic reference switching between DCO and DPLL modes to simplify support for an external phase/time input Internal customer definable One-Time Programmable (OTP) interface in a T-BC memory with up to 16 different configurations 2 2 Generates output frequencies that are independent of input Standard external I C EPROM via separate I C Master Port frequencies via a Fractional Output Divider (FOD) 1149.1 JTAG Boundary Scan Each FOD supports output phase tuning with 1ps resolution 10 10 mm (with 0.8mm ball pitch) 144-CABGA package 2021 Renesas Electronics Corporation 1 November 25, 20218A34001 Datasheet 1 Block Diagram Figure 1. Block Diagram XO DPLL OSCI OSCO To FODs System Osc FOD DPLL System APLL Combo Bus Div Out Q0 DPLL/ FOD CLK0 DCO 0 Q1 Div Out Div Out Q2 CLK1 DPLL/ FOD DCO 1 Div Out Q3 CLK2 Reference Div Out Q4 DPLL/ Monitors FOD DCO 2 Div Out Q5 CLK3 Reference Switching Div Out Q6 DPLL/ FOD State DCO 3 CLK4 Q7 Div Out Machines DPLL/ FOD Div Out Q8 PWM DCO 4 CLK5 Decoders DPLL/ FOD Div Out Q9 DCO 5 CLK6 DPLL/ FOD Div Out Q10 DCO 6 CLK7 DPLL/ FOD Div Out Q11 DCO 7 Status and Configuration OTP Registers PWM 2 2 2 I C Master SPI/I C 0 SPI/I C 1 GPIO / JTAG Encoders Description The 8A34001 is a Synchronization Management Unit (SMU) for packet-based and physical layer based equipment synchronization. The device is a highly integrated device that provides tools to manage timing references, clock sources and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital Phase Lock Loops (DPLL). The 8A34001 supports multiple independent timing paths that can each be configured as a DPLL or as a DCO. Input-to-input, input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize interfaces such as 100GBASE-R, 40GBASE-R, 10GBASE-R, and 10GBASE-W and lower-rate Ethernet interfaces as well as SONET/SDH and PDH interfaces, and IEEE 1588 Time Stamp Units (TSUs). 1 This device is covered by one or more of the following patents: US 9,369,270, US 10,355,699, US 10,075,284, US 9,628,255, and US 9,479,182. 2021 Renesas Electronics Corporation 2 November 25, 2021