8A34002 Datasheet Synchronization Management Unit 8 Differential / 16 LVCMOS outputs Overview Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS) The 8A34002 Synchronization Management Unit (SMU) provides Jitter below 150fs RMS (10kHz to 20MHz) tools to manage timing references, clock sources, and timing LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL paths for IEEE 1588 and Synchronous Ethernet (SyncE) based output modes supported clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators Differential output swing is selectable: 400mV / 650mV / 800mV / 910mV (DCO), or Digital Phase Lock Loops (DPLL). Independent output voltages of 3.3V, 2.5V, or 1.8V Optional clock recovery filter/servo software is available under LVCMOS additionally supports 1.5V or 1.2V license from Renesas for use with the 8A34002. The filter/servo The clock phase of each output is individually programmable software is designed to suppress the affects of Packet Delay in 1ns to 2ns steps with a total range of 180 Variation (PDV) on packet based timing signals it can be used with protocol stacks for IEEE 1588 or other packet-based timing 7 differential / 14 single-ended clock inputs protocols. Support frequencies from 0.5Hz to 1GHz Any input can be mapped to any or all of the timing channels Typical Applications Redundant inputs frequency independent of each other Any input can be designated as external frame/sync pulse of Core and access IP switches / routers EPPS (even pulse per second), 1 PPS (Pulse per Second), Synchronous Ethernet equipment 5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz Telecom Boundary Clocks (T-BCs) and Telecom Time Slave associated with a selectable reference clock input Clocks (T-TSCs) according to ITU-T G.8273.2 Per-input programmable phase offset of up to 1.638 s in 10Gb, 40Gb, and 100Gb Ethernet interfaces 1ps steps Central Office Timing Source and Distribution Reference monitors qualify/disqualify references depending on Wireless infrastructure for 4.5G and 5G network equipment LOS, activity, frequency monitoring, and/or LOS input pins Loss of Signal (LOS) input pins (via GPIOs) can be assigned Features to any input clock reference Automatic reference selection state machines select the active Four independent timing channels reference for each DPLL based on the reference monitors, Each can act as a frequency synthesizer, jitter attenuator, priority tables, revertive / non-revertive, and other Digitally Controlled Oscillator (DCO), or Digital Phase Lock programmable settings Loop (DPLL) System APLL operates from fundamental-mode crystal: 25MHz DPLLs generate telecom compliant clocks to 54MHz or from a crystal oscillator Compliant with ITU-T G.8262 for Synchronous Ethernet System DPLL accepts an XO, TCXO, or OCXO operating at Compliant with legacy SONET/SDH and PDH virtually any frequency from 1MHz to 150MHz requirements DPLLs can be configured as DCOs to synthesize Precision DPLL Digital Loop Filters (DLFs) are programmable with cut Time Protocol (PTP) / IEEE 1588 clocks off frequencies from 12Hz to 22kHz DCOs generate PTP based clocks with frequency resolution DPLL/DCO channels share frequency information using the -16 less than 1.11 10 Combo Bus to simplify compliance with ITU-T G.8273.2 DPLL Phase detectors can be used as Time-to-Digital Switching between DPLL and DCO modes is hitless and Converters (TDC) with precision below 1ps dynamic 2 Supports 1MHz I C or 50MHz SPI serial processor ports Automatic reference switching between DCO and DPLL The device can configure itself automatically after reset via: modes to simplify support for an external phase/time input Internal customer definable One-Time Programmable interface in a T-BC memory with up to 16 different configurations Generates output frequencies that are independent of input 2 2 Standard external I C EPROM via separate I C Master Port frequencies via a Fractional Output Divider (FOD) 1149.1 JTAG Boundary Scan Each FOD supports output phase tuning with 1ps resolution 10 10 mm 72-VFQFN package 2020 Renesas Electronics Corporation 1 September 8, 20208A34002 Datasheet Block Diagram Figure 1. Block Diagram XO DPLL OSCI OSCO To FODs System Osc FOD DPLL System APLL Combo Bus (Frequency Data) Div Q0 CLK0 DPLL / FOD DCO 0 Div Q1 CLK1 Reference Div Q2 Monitors CLK2 DPLL / FOD DCO 1 Reference Div Q3 Switching CLK3 State Machines Div Q4 CLK4 DPLL / PWM FOD DCO 2 Decoders Div Q5 CLK5 Div Q6 CLK6 DPLL / FOD DCO 3 Div Q7 Status and Configuration OTP Registers 2 2 I C Master SPI/I C PWM Encoders GPIO / JTAG Description The 8A34002 is a Synchronization Management Unit (SMU) for packet based and physical layer based equipment synchronization. The 8A34002 is a highly integrated device that provides tools to manage timing references, clock sources, and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital Phase Lock Loops (DPLL). The 8A34002 supports multiple independent timing paths that can each be configured as a DPLL or as a DCO. Input-to-input, input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize interfaces such as 100GBASE-R, 40GBASE-R, 10GBASE-R, 10GBASE-W, and lower-rate Ethernet interfaces as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs). The internal System APLL must be supplied with a low phase noise reference clock with frequency between 25MHz and 54MHz. The output of the System APLL is used for clock synthesis by all of the Fractional Output Dividers (FODs) in the device. The System APLL reference can come from an external crystal oscillator connected to the OSCI pin or from an internal oscillator that uses a crystal connected between the OSCI and OSCO pins. 2020 Renesas Electronics Corporation 2 September 8, 2020