Port Synchronizer for IEEE 1588 8A34012 Datasheet Frequency and Time/Phase 7 differential / 14 single-ended clock inputs Overview Support frequencies from 1kHz to 1GHz The 8A34012 is a port synchronizer for frequency and time/phase Any input can be mapped to any or all of the timing channels for equipment that uses packet-based and physical layer-based Redundant inputs frequency independent of each other equipment synchronization. Any input can be designated as external frame/sync pulse of The 8A34012 is a highly integrated device that provides tools to EPPS (even pulse per second), 1 PPS (Pulse per Second), manage timing references, clock sources, and timing paths for 5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The associated with a selectable reference clock input PLL channels can act independently as frequency synthesizers, Per-input programmable phase offset of up to 1.638 s in jitter attenuators, Digitally Controlled Oscillators (DCO) or Digital 1ps steps Phase Lock Loops (DPLL). Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins Typical Applications Loss of Signal (LOS) input pins (via GPIOs) can be assigned Core and access IP switches / routers to any input clock reference Synchronous Ethernet equipment Automatic reference selection state machines select the active Telecom Boundary Clocks (T-BCs) and Telecom Time Slave reference for each DPLL based on the reference monitors, Clocks (T-TSCs) according to ITU-T G.8273.2 priority tables, revertive / non-revertive, and other programmable settings 10Gb, 40Gb and 100Gb Ethernet interfaces System APLL operates from fundamental-mode crystal: 25MHz Central Office Timing Source and Distribution to 54MHz or from a crystal oscillator Wireless infrastructure for 4.5G and 5G network equipment System DPLL accepts an XO, TCXO, or OCXO operating at virtually any frequency from 1MHz to 150MHz Features DPLLs can be configured as DCOs to synthesize Precision Four independent timing channels Time Protocol (PTP) / IEEE 1588 clocks Each can act as a frequency synthesizer, jitter attenuator, DCOs generate PTP based clocks with frequency resolution -16 Digitally Controlled Oscillator (DCO), or Digital Phase Lock less than 1.11 10 Loop (DPLL) DPLL Phase detectors can be used as Time-to-Digital DPLL Digital Loop Filters (DLFs) are programmable with Converters (TDC) with precision below 1ps cut-off frequencies from 17Hz to 22kHz 2 Supports 1MHz I C or 50MHz SPI serial processor ports Switching between DPLL and DCO modes is hitless and Can configure itself automatically after reset via: dynamic Internal customer definable One-Time Programmable Generates output frequencies that are independent of input memory with up to 16 different configurations frequencies via a Fractional Output Divider (FOD) 2 2 Standard external I C EPROM via separate I C Master Port Each FOD supports output phase tuning with 1ps resolution 1149.1 JTAG Boundary Scan 8 Differential / 16 LVCMOS outputs 10 10 mm, 72-QFN package Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS) Jitter below 150fs RMS (10kHz to 20MHz) LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL output modes supported Differential output swing is selectable: 400mV / 650mV / 800mV / 910mV Independent output voltages of 3.3V, 2.5V, or 1.8V LVCMOS additionally supports 1.5V or 1.2V The clock phase of each output is individually programmable in 1ns to 2ns steps with a total range of 180 2020 Renesas Electronics Corporation 1 September 8, 20208A34012 Datasheet Block Diagram Figure 1. Block Diagram XO DPLL OSCI OSCO To FODs System Osc FOD DPLL System APLL Combo Bus (Frequency Data) Div Q0 CLK0 DPLL / FOD DCO 0 Div Q1 CLK1 Reference Div Q2 Monitors CLK2 DPLL / FOD DCO 1 Reference Div Q3 Switching CLK3 State Machines Div Q4 CLK4 DPLL / PWM FOD DCO 2 Decoders Div Q5 CLK5 Div Q6 CLK6 DPLL / FOD DCO 3 Div Q7 Status and Configuration OTP Registers 2 2 I C Master SPI/I C PWM Encoders GPIO / JTAG Description The 8A34012 is a port synchronizer for frequency and time/phase for equipment that uses packet based and physical layer based equipment synchronization. The 8A34011 is a highly integrated device that provides tools to manage timing references, clock sources and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital Phase Lock Loops (DPLL). The 8A34012 supports multiple independent timing paths that can each be configured as a DPLL or as a DCO. Input-to-input, input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize interfaces such as 100GBASE-R, 40GBASE-R, 10GBASE-R, and 10GBASE-W and lower-rate Ethernet interfaces as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs). The internal System APLL must be supplied with a low phase noise reference clock with frequency between 25MHz and 54MHz. The output of the System APLL is used for clock synthesis by all of the Fractional Output Dividers (FODs) in the device. The System APLL reference can come from an external crystal oscillator connected to the OSCI pin or from an internal oscillator that uses a crystal connected between the OSCI and OSCO pins. 2020 Renesas Electronics Corporation 2 September 8, 2020