Quad-Frequency IDT8N0QV01 Rev H Programmable VCXO DATASHEET General Description Features The 8N0QV01 is a Quad-Frequency ProgrammableVCXO with very Fourth generation FemtoClock NG technology flexible frequency and pull-range programming capabilities.The Programmable clock output frequency from device uses IDTs Fourth Generation FemtoClock NG technology 15.476MHz to 260MHz for an optimum of high clock frequency and low phase noise Fourpower-updefaultfrequencies(seepartnumberordercodes), performance.The device accepts 2.5V or 3.3V supply and is 2 re-programmable by I C packaged in a small, lead-free (RoHS 6) 10-lead ceramic 5mm x 2 I C programming interface for the output clock frequency, APR 7mm x 1.55mm package. and internal PLL control registers Besides the four default power-up frequencies set by the FSEL0 and 2 Frequency programming resolution is 435.9Hz N FSEL1 pins, the 8N0QV01 can be programmed via the I C interface to any output clock frequency between 15.476MHz to 260MHz to a Absolute pull-range (APR) programmable from very high degree of precision with a frequency step size of 435.9Hz 2.5 to 727.5ppm N (N: PLL post divider). Since the FSEL0 and FSEL1 pins are One 2.5V, 3.3V LVCMOS clock output mapped to four independent PLL, P, M and N divider registers (P, Two control inputs for the power-up default frequency MINT, MFRAC and N), reprogramming those registers to other frequencies under control of FSEL0 and FSEL1 is supported.The LVCMOS/LVTTL compatible control inputs extended temperature range supports wireless infrastructure, RMS phase jitter 156.25MHz telecommunication and networking end equipment requirements. (12kHz - 20MHz): 0.635ps (typical) RMS phase jitter 156.25MHz (1kHz - 40MHz): 0.850ps (typical) 2.5V or 3.3V supply voltage modes -40C to 85C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram Pin Assignment PFD FemtoClock NG P OSC & VCO N Q 10 9 LPF 1950-2600MHz VDD VC 1 8 114.285MHz GND 3 6 Q MINT, MFRAC 4 5 2 A/D VC 7 7 25 Pulldown FSEL1 Configuration Register (ROM) IDT8N0QV01 Rev H Pulldown FSEL0 (Frequency, APR, Polarity) 10-lead ceramic 5mm x 7mm x 1.55mm package body Pullup SCLK 2 I C Control Pullup CD Package SDATA TopView Pullup OE IDT8N0QV01HCD REVISION A MARCH 13, 2014 1 2013 Integrated Device Technology, Inc. FSEL0 SCLK FSEL1 SDATAIDT8N0QV01 Rev H Data Sheet QUAD-FREQUENCY PROGRAMMABLE-VCXO Block Diagram with Programming Registers Output Divider N PFD FemtoClock NG P OSC N & VCO LPF 1950-2600MHz 114.285MHz 2 Feedback Divider M (25 Bit) 7 MINT MFRAC (7 bits) (18 bits) VC A/D 7 7 18 34 Programming Registers ADC GAIN ADC POL 41 2 2 I C Control I C: 6 bits 1 bit Def: 6 bits 1 bit 7 7 P0 MINT0 MFRAC0 N0 2 I C: 2 bits 7 bits 18 bits 7 bits 00 Def: 2 bits 7 bits 18 bits 7 bits 30 34 P1 MINT1 MFRAC1 N1 2 I C: 2 bits 7 bits 18 bits 7 bits 01 Def: 2 bits 7 bits 18 bits 7 bits 30 34 P2 MINT2 MFRAC2 N2 34 2 Pullup I C: 2 bits 7 bits 18 bits 7 bits SCLK 10 Pullup Def: 2 bits 7 bits 18 bits 7 bits SDATA 30 34 P3 MINT3 MFRAC3 N3 2 I C: 2 bits 7 bits 18 bits 7 bits 11 Def: 2 bits 7 bits 18 bits 7 bits 30 34 Pulldown, Pulldown FSEL 1:0 Pullup OE 2 Def: Power-up default register setting for I C registers ADC GAINn, ADC POL, Pn, MINTn, MFRACn and Nn IDT8N0QV01HCD REVISION A MARCH 13, 2014 2 2013 Integrated Device Technology, Inc.