Quad-Frequency Programmable XO IDT8N3Q001 REV G DATA SHEET General Description Features The IDT8N3Q001 is a Quad-Frequency Programmable Clock Fourth generation FemtoClock NG technology Oscillator with very flexible frequency programming capabilities. The Programmable clock output frequency from 15.476MHz to device uses IDTs fourth generation FemtoClock NG technology for 866.67MHz and from 975MHz to 1,300MHz an optimum of high clock frequency and low phase noise Four power-up default frequencies (see part number order 2 performance. The device accepts 2.5V or 3.3V supply and is codes), re-programmable by I C packaged in a small, lead-free (RoHS 6) 10-lead Ceramic 5mm x 2 I C programming interface for the output clock frequency and 7mm x 1.55mm package. internal PLL control registers Besides the four default power-up frequencies set by the FSEL0 and Frequency programming resolution is 435.9Hz N 2 FSEL1 pins, the IDT8N3Q001 can be programmed via the I C One 2.5V, 3.3V LVPECL clock output interface to output clock frequencies between 15.476MHz to Two control inputs for the power-up default frequency 866.67MHz and from 975MHz to 1,300MHz to a very high degree of LVCMOS/LVTTL compatible control inputs precision with a frequency step size of 435.9Hz N (N is the PLL output divider). Since the FSEL0 and FSEL1 pins are mapped to 4 RMS phase jitter 156.25MHz (12kHz - 20MHz): 0.244ps independent PLL M and N divider registers (P, MINT, MFRAC and N), (typical), integer PLL feedback configuration reprogramming those registers to other frequencies under control of RMS phase jitter 156.25MHz (1kHz - 40MHz): 0.265ps FSEL0 and FSEL1 is supported. The extended temperature range (typical), integer PLL feedback configuration supports wireless infrastructure, telecommunication and networking Full 2.5V or 3.3V supply modes end equipment requirements. -40C to 85C ambient operating temperature Available in Lead-free (RoHS 6) package Block Diagram Pin Assignment PFD FemtoClock NG Q P OSC N & VCO nQ LPF 1950-2600MHz DNU 1 8 V CC f XTAL OE 2 7 nQ V 3 6 Q MINT, MFRAC EE 2 25 7 Pulldown FSEL1 Configuration Register (ROM) Pulldown IDT8N3Q001 FSEL0 (Frequency, APR, Polarity) 10-lead Ceramic 5mm x 7mm x 1.55mm Pullup package body SCLK 2 I C Control Pullup CD Package SDATA Top View Pullup OE IDT8N3Q001GCD REVISION A MARCH 6, 2012 1 2012 Integrated Device Technology, Inc. FSEL0 4 10 SCLK FSEL1 5 9 SDATAIDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Table 1. Pin Descriptions Number Name Type Description 1 DNU Unused Do not use. Output enable pin. See Table 3 for function. LVCMOS/LVTTL interface 2 OE Input Pullup levels. 3V Power Negative power supply. EE Default frequency select pins. See the Default Frequency Order Codes 5, 4 FSEL1, FSEL0 Input Pulldown section. LVCMOS/LVTTL interface levels. 6, 7 Output Differential clock output. LVPECL interface levels. Q, nQ 8 Power Power supply pin. V CC 2 I C Data Input/Output. Input: LVCMOS/LVTTL compatible interface levels. 9 Input/Output Pullup SDATA Output: Open drain. 2 10 Input Pullup SCLK I C Clock Input. LVCMOS/LVTTL compatible interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 5.5 pF IN R Input Pullup Resistor 50 k PULLUP R Input Pulldown Resistor 50 k PULLDOWN Function Tables Table 3A. OE Configuration Input OE Output Enable 0 Outputs Q, nQ are in high-impedance state. 1 (default) Outputs are enabled. NOTE: OE is an asynchronous control. Table 3B. Output Frequency Range 15.476MHz to 866.67MHz 975MHz to 1,300MMHz NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of 218Hz or better. IDT8N3Q001GCD REVISION A MARCH 6, 2012 2 2012 Integrated Device Technology, Inc.