FemtoClock NG Octal Universal 8T49N285 Datasheet Frequency Translator Description Features The 8T49N285 has a fractional-feedback PLL that can be used as a Supports SDH/SONET and Synchronous Ethernet clocks including all FEC rate conversions jitter attenuator or frequency translator. It is equipped with six integer and two fractional output dividers, allowing the generation of up to 8 <0.3ps RMS typical jitter (including spurs),12kHz to 20MHz different output frequencies, ranging from 8kHz to 1GHz. Three of Operating modes: locked to input signal, holdover and free-run these frequencies are completely independent of each other and the Initial holdover accuracy of 50ppb inputs. The other five are related frequencies. The eight outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels. Accepts two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS input clocks This functionality makes it ideal to be used in any frequency translation application, including 1G, 10G, 40G, and 100G Accepts frequencies ranging from 8kHz up to 875MHz Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T Auto and manual input clock selection with hitless switching G.709 (2009) FEC rates. The device may also behave as a frequency Clock input monitoring, including support for gapped clocks synthesizer. Phase-Slope Limiting and Fully Hitless Switching options to The 8T49N285 accepts up to two differential or single-ended input control output phase transients clocks and a crystal input. The PLL can lock to either input clock, but both input clocks must be related in frequency. Operates from a 10MHz to 40MHz fundamental-mode crystal The device supports hitless reference switching between input Generates 8 LVPECL/LVDS/HCSL or 16 LVCMOS output clocks clocks. The device monitors both input clocks for Loss of Signal Output frequencies ranging from 8kHz up to 1.0GHz (diff) (LOS). It generates an alarm when an input clock failure is detected. Output frequencies ranging from 8kHz to 250MHz (LVCMOS) Automatic and manual hitless reference switching options are supported. LOS behavior can be set to support gapped or un-gapped Four General Purpose I/O pins with optional support for status & clocks. control: The 8T49N285 supports holdover with an initial accuracy of 50ppB Four Output Enable control inputs may be mapped to any of the from the point where the loss of all applicable input reference(s) has eight outputs been detected. It maintains a historical average operating point that Lock, Holdover & Loss-of-Signal status outputs may be returned to in holdover at a limited phase slope. Open-drain Interrupt pin The device places no constraints on input to output frequency Nine programmable PLL loop bandwidth settings from 1.4Hz to conversion, supporting all FEC rates, including the new revision of 360Hz. ITU-T Recommendation G.709 (2009), most with 0ppm conversion error. Optional Fast Lock function The PLL has a register-selectable loop bandwidth from 1.4Hz to Programmable output phase delays in steps as small as 16ps 360Hz. 2 2 Register programmable through I C or via external I C EEPROM Each output supports individual phase delay settings to allow Bypass clock paths for system tests output-output alignment. Power supply modes The device supports Output Enable inputs and Lock, Holdover and V / V / V CC CCA CCO LOS status outputs. 3.3V / 3.3V / 3.3V 2 The device is programmable through an I C interface. It also supports 3.3V / 3.3V / 2.5V 2 I C master capability to allow the register configuration to be read 3.3V / 3.3V / 1.8V (LVCMOS) from an external EEPROM. 2.5V / 2.5V / 3.3V 2.5V / 2.5V / 2.5V 2.5V / 2.5V / 1.8V (LVCMOS) Typical Applications -40C to 85C ambient operating temperature OTN or SONET / SDH equipment Line cards (up to OC-192, and Package: 56QFN, lead-free RoHs (6) supporting FEC ratios) OTN de-mapping (Gapped Clock and DCO mode) Gigabit and Terabit IP switches / routers including support of Synchronous Ethernet SyncE (G.8262) applications Wireless base station baseband Data communications 100G Ethernet 2021 Renesas Electronics Corporation. 1 March 8, 20218T49N285 Datasheet 8T49N285 Block Diagram XTAL IntN Output OSC Q0 Input Clock Fractional Divider Monitoring, Feedback Priority, APLL IntN Output CLK0 P0 Q1 & Divider Lock CLK1 P1 Selection Holdover FracN Output Q2 Divider FracN Output Q3 Divider IntN Q4 Reset nRST LOS IntN Q5 Logic Status Registers GPIO OTP Logic 2 IntN I C Master Q6 Control Registers SCLK 4 2 I C Slave SDATA Q7 IntN Serial EEPROM PLL BYP SA0 GPIO nINT Figure 1. 8T49N285 Functional Block Diagram 2021 Renesas Electronics Corporation. 2 March 8, 2021