FemtoClock NG Octal Universal 8T49N287 Frequency Translator Datasheet Description Features The 8T49N287 has two independent, fractional-feedback PLLs that Supports SDH/SONET and Synchronous Ethernet clocks can be used as jitter attenuators and frequency translators. It is including all FEC rate conversions equipped with six integer and two fractional output dividers, allowing <0.3ps RMS Typical jitter (including spurs), 12kHz to 20MHz the generation of up to 8 different output frequencies, ranging from Operating modes: locked to input signal, holdover and free-run 8kHz to 1GHz. Four of these frequencies are completely independent Initial holdover accuracy of 50ppb of each other and the inputs. The other four are related frequencies. The eight outputs may select among LVPECL, LVDS, HCSL, or Accepts up to two LVPECL, LVDS, LVHSTL, HCSL, or LVCMOS LVCMOS output levels. input clocks Accepts frequencies ranging from 8kHz up to 875MHz This makes it ideal to be used in any frequency translation application, including 1G, 10G, 40G and 100G Synchronous Auto and manual input clock selection with hitless switching Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC Clock input monitoring, including support for gapped clocks rates. The device may also behave as a frequency synthesizer. Phase-Slope Limiting and Fully Hitless Switching options to The 8T49N287 accepts up to two differential or single-ended input control output phase transients clocks and a crystal input. Each of the two internal PLLs can lock to Operates from a 10MHz to 40MHz fundamental-mode crystal different input clocks which may be of independent frequencies. Each Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output clocks PLL can use the other input for redundant backup of the primary clock, but in this case, both input clocks must be related in frequency. Output frequencies ranging from 8kHz up to 1.0GHz (diff) Output frequencies ranging from 8kHz to 250MHz (LVCMOS) The device supports hitless reference switching between input clocks. The device monitors all input clocks for Loss of Signal (LOS), and Four General Purpose I/O pins with optional support for status & generates an alarm when an input clock failure is detected. Automatic control: and manual hitless reference switching options are supported. LOS Four Output Enable control inputs may be mapped to any of the behavior can be set to support gapped or un-gapped clocks. eight outputs The 8T49N287 supports holdover for each PLL. The holdover has an Lock, Holdover and Loss-of-Signal status outputs initial accuracy of 50ppB from the point where the loss of all Open-drain Interrupt pin applicable input reference(s) has been detected. It maintains a Nine programmable loop bandwidth settings for each PLL from historical average operating point for each PLL that may be returned 1.4Hz to 360Hz to in holdover at a limited phase slope. Optional Fast Lock function The device places no constraints on input to output frequency conver- Programmable output phase delays in steps as small as 16ps sion, supporting all FEC rates, including the new revision of ITU-T Rec- 2 2 ommendation G.709 (2009), most with 0ppm conversion error. Register programmable through I C or via external I C EEPROM Each PLL has a register-selectable loop bandwidth from 1.4Hz to Bypass clock paths for system tests 360Hz. Power supply modes V / V / V Each output supports individual phase delay settings to allow CC CCA CCO 3.3V / 3.3V / 3.3V output-output alignment. 3.3V / 3.3V / 2.5V The device supports Output Enable inputs and Lock, Holdover and 3.3V / 3.3V / 1.8V (LVCMOS) LOS status outputs. 2.5V / 2.5V / 3.3V 2 2.5V / 2.5V / 2.5V The device is programmable through an I C interface. It also supports 2 2.5V / 2.5V / 1.8V (LVCMOS) I C master capability to allow the register configuration to be read from an external EEPROM. -40C to 85C ambient operating temperature Package: 56QFN, lead-free (RoHS 6) Typical Applications OTN or SONET / SDH equipment Line cards (up to OC-192, and supporting FEC ratios) OTN de-mapping (Gapped Clock and DCO mode) Gigabit and Terabit IP switches / routers including support of Synchronous Ethernet SyncE (G.8262) applications Wireless base station baseband Data communications 100G Ethernet 2021 Renesas Electronics Corporation. 1 March 8, 20218T49N287 Datasheet 8T49N287 Block Diagram IntN Output Q0 Fractional Divider Feedback XTAL APLL 0 IntN Output OSC Q1 Divider Lock 0 Input Clock Holdover 0 Monitoring, FracN Output CLK0 P0 Q2 Priority, Fractional Divider & CLK1 P1 Feedback Selection APLL 1 FracN Output Q3 Divider Lock 1 Holdover 1 IntN Q4 Reset nRST LOS IntN Q5 Logic Status Registers GPIO Logic OTP 2 IntN Q6 I C Master Control Registers SCLK 4 2 I C Slave SDATA IntN Q7 Serial EEPROM PLL BYP SA0 nINT GPIO Figure 1. 8T49N287 Functional Block Diagram 2021 Renesas Electronics Corporation. 2 March 8, 2021