FemtoClock NG Jitter Attenuator and 8V19N408
Clock Synthesizer
DATA SHEET
General Description Features
8V19N408 is a fully integrated FemtoClock NG Jitter Attenuator and Core timing unit for JESD204B wireless infrastructure clocks
Clock Synthesizer. The device is a high-performance clock solution
Fourth generation FemtoClock NG technology
for conditioning and frequency/phase management of wireless base
First stage PLL uses an external VCXO for jitter attenuation
station radio equipment boards and is optimized to deliver excellent
Second PLL stage facilitates a dual integrated VCO for flexible
phase noise performance. The device supports JESD204B subclass
frequency synthesis
0 and 1 clock implementations. The device is very flexible in
Integrated VCO frequencies: 2400MHz - 2500MHz (VCO-0) and
programming of the output frequency and phase. A two-stage PLL
2920MHz - 3000MHz (VCO-1)
architecture supports both jitter attenuation and frequency
Five differential configurable LVPECL, LVDS clock outputs with a
multiplication. The first stage PLL is the jitter attenuator and uses an
variable output amplitude
external VCXO for best possible phase noise characteristics.The
Four differential LVDS system reference (SYSREF) signal outputs
second stage PLL lock on the VCXO-PLL output signal and
Synchronization between clock and system reference signals
synthesizes the target frequency. For flexibility, the second-stage PLL
Wide input frequency range supported by 8-bit pre- and 15-bit
can use one of two VCOs at 2400MHz - 2500MHz (VCO-0) and
VCOX-PLL feedback divider
2920MHz - 3000MHz (VCO-1).
Output clock frequencies: 2457.6MHz N (VCO-0) and
The device supports the clock generation of high-frequency clocks
2949.12MHz N (VCO-1) in wireless infrastructure applications
from the selected VCO and low-frequency system reference signals
Three independent output clock frequency dividers N (range of 1
(SYSREF). The system reference signals are internally synchronized
to 96)
to the clock signals. Delay functions exist for achieving alignment and
Clock output frequency range (VC0-0): (2400MHz - 2500MHz) N
controlled phase delay between system reference and clock signals
Clock output frequency range (VC0-1): (2920MHz - 3000MHz) N
and to align/delay individual output signals. The input is monitored for
Phase delay capabilities for alignment/delay for clock and
activity. Short-term hold-over is provided to handle clock input failure
SYSREF signals
scenarios. Auto-lock, individually programmable output frequency
Individual output phase adjustment (Clock): one-period of the
dividers and phase adjustment capabilities are added for flexibility.
selected VCO frequency in 64 steps
The device is configured through a 4-wire SP serial interface and
Individual output phase adjustment (SYSREF): approximately
reports lock and signal loss status in internal registers and optionally
half-period of the selected VCO frequency in 8 steps
via lock detect (nINT) output. The device is packaged in a lead-free
(RoHS 6) 72-lead VFQFN package. The extended temperature range Internal, SPI controlled SYSREF pulse generation
supports wireless infrastructure, telecommunication and networking
SYSREF frequencies: f N (10 dividers)
VCO S
end equipment requirements. The device is a member of the
N divider range: 64 to 2048
S
high-performance clock family from IDT.
SYSREF (wireless infrastructure): 1.2MHz 46.08MHz
Clock input compatible with LVPECL, LVDS, LVCMOS signals
Dedicated power-down features for reducing power consumption
Input clock monitoring
Holdover for temporary loss of input signal scenarios
Support of output power-down and output disable
Typical clock output phase noise at 1228.8MHz:
1kHz offset: -116.9dBc/Hz
10kHz offset: -118.1dBc/Hz
100kHz offset: -122.7dBc/Hz
1MHz offset: -144.7dBc/Hz
10MHz offset: -153.5dBc/Hz
RMS phase noise (12kHz 20MHz): <100fs (target)
Status conditions with programmable functionality for loss-of-lock
and loss-of-reference indication
Lock detect (nINT) output for status change indication
LVCMOS/LVTTL compatible SPI serial interface
3.3V core and output supply mode
Control pins support 3.3V I/O logic levels:
SPI interface levels support selectable 3.3V/1.8V logic levels
-40C to +85C ambient operating temperature
Lead-free (RoHS 6) 72-lead VFQFN packaging
REVISION 2 10/1/15 1 2015 INTEGRATED DEVICE TECHNOLOGY, INC.8V19N408 DATA SHEET
Block Diagram
C C C C
01 11
02 12
R R
f
0 1
VCXO
C C
V1
V0
R
V
nVCXO
VCXO
LFV
QVCXO
nQVCXO
VCXO-PLL
VCO-0
PFD
F0
2457.6 MHz
C0
1
M
0
CLK Clock F0
C0R
0
P 8 Bit
V
Monitor
nCLK
8 Bit
C1
PFD
BYPASS
VCO-1
V
1
PFD
F1
2949.12 MHz
M
V
C1R
SEL
15 Bit
M
F1
8 Bit
Dual VCO
Holdover
FemtoClock NG
Control
QCLKA0
nQCLKA0
CLK
A
SYSREF QCLKA1
N
N
S
A A
Control
nQCLKA1
Delay Divider
0
QREFA0
QREF MUX
A0
1
nQREFA0
A0
0
QREFA1
QREF MUX
A1
1
nQREFA1
A1
QCLKB0
nQCLKB0
CLK
B
QCLKB1
B N
B
nQCLKB1
SPICLK
Delay Divider
0
MOSI
QREFB0
QREF MUX
B0
MISO SPI Slave
1
nQREFB0
B0
Register File
Controller
nLE
nINT
0
QREFB1
QREF MUX
B1
SELSV
1
nQREFB1
B1
CLK
C
QCLKC
C N
C
nQCLKC
Delay Divider
8V19N408
FEMTOCLOCK NG JITTER ATTENUATOR AND 2 REVISION 2 10/1/15
CLOCK SYNTHESIZER
VCO0R
VCO0
LF0
LF1
VCO1
VCO1R