Crystal-to-HCSL 100MHz PCI EXPRESS IDT8V41S104I
Clock Synthesizer
DATA SHEET
General Description Features
The IDT8V41S104I is a PLL-based clock generator specifically
Four 0.7V current mode differential HCSL output pairs
designed for PCI EXPRESS Generation 3 applications. This
One 0.7V current mode differential HCSL reference output
device generates a 100MHz differential HCSL clock from an input
reference of 25MHz. The input reference may be derived from an
CLK, nCLK input can accept the following input levels: HCSL,
external source or by the addition of a 25MHz crystal to the on-chip LVDS, LVPECL, LVHSTL
crystal oscillator. The device offers spread spectrum clock output for
Crystal oscillator interface: 25MHz
reduced EMI applications. The spread spectrum control pins are
Output frequency: 100MHz
used to enable or disable spread spectrum operation, as well as
selecting either a down spread value of -0.35% or -0.5%. The enable RMS phase jitter @ 100MHz (12kHz 20MHz): 1.2ps (typical)
and disable for each of the outputs is controlled via individual output
Spread Spectrum for electromagnetic interference (EMI) reduction
enable pins. The IDT8V41S104I is packaged in a compact, lead-free
Individual output control via output enable pins
(RoHS 6) 32-lead VFQFN package. The industrial temperature
range supports high end computing, telecommunication and In bypass mode functions as a 1 to 5 fanout buffer
networking end equipment requirements.
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
3.3V operating supply mode
-40C to 85C ambient operating temperature
Available lead-free (RoHS 6) package
Pin Assignment
24 23 22 21 20 19 18 17
25
V 16 V
DD DDA
26
Q3 15 PLL_BYPASS
nQ3 27 14 SSC_ENABLE
28
OE3 13 SSC_0.5DN
29 12
OE2 CLK_SEL
Q2 30 11 OE_REF
31
10 IREF
nQ2
32 9
GND V
DD
12 3 4 5 6 7 8
IDT8V41S104I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm ePad size
NL Package
Top View
IDT8V41S104I REVISION B MAY 6, 2014 1 2014 Integrated Device Technology, Inc.
GND
V
DD
nCLK
Q1
CLK
nQ1
XTAL_OUT
OE1
XTAL_IN
OE0
VDD
Q0
nREF_OUT
nQ0
REF_OUT
GNDIDT8V41S104I DATA SHEET
Block Diagram
Pulldown
OE_REF
REF_OUT
nREF_OUT
Pulldown
Q0
CLK SEL
nQ0
25MHz
1
Q1
XTAL_IN
OSC 0 nQ1
Divider
XTAL_OUT
Q2
PLL
0
Network
Pulldown
nQ2
CLK
1
PU/PD
nCLK
Q3
nQ3
IREF
Pullup
SSC_0.5DN
SSC
Pulldown
Control
SSC_ENABLE
Pulldown
PLL_BYPASS
Pulldown
OE0
Pulldown
OE1
Pulldown
OE2
Pulldown
OE3
CRYSTAL-TO-HCSL 100MHZ PCI EXPRESS CLOCK SYNTHESIZER 2 REVISION B MAY 6, 2014