10G Ethernet PLL and IEEE 1588 Short Form Datasheet Synthesizer for Industrial Automa- IDT8V89317 Internal DCO has resolution of 0.01105 ppb and can be controlled FEATURES by an external processor via I2C interface for IEEE 1588 clock gen- HIGHLIGHTS eration Digital PLL locks to GPS or Ethernet physical layer clocks Two Analog PLLs for jitter attenuation and frequency translation Provides clocks for 1 Gigabit and 10 Gigabit Ethernet, QSGMII and IN1, IN2 and IN3 accept single ended reference clocks whose fre- XAUI quencies can be 1PPS (1 Hz), 25 MHz, 125 MHz or 156.25 MHz Internal Digitally Controlled Oscillator supports IEEE 1588 clocks OUT1 and OUT2 output differential clocks with frequencies of 125 generation MHz or 156.25 MHz Jitter generation <0.3ps RMS (10 kHz to 20 MHz), meets jitter OUT3 outputs a differential clock with frequency of requirements of leading PHYs supporting 10GBASE-R, QSGMII 322.265625 MHz or 644.53125 MHz and XAUI OUT4 outputs a free-running LVCMOS clock with frequency of 25 MHz MAIN FEATURES Digital PLL synchronizes with GPS or Ethernet connected synchro- OTHER FEATURES nization sources I2C microprocessor interface mode DPLL bandwidth is selectable to be 15 mHz or 1.2 Hz IEEE 1149.1 JTAG Boundary Scan DPLL holdover accuracy is 1.1X10-5 ppm and instantaneous hold- 1mm ball pitch CABGA green package over accuracy is 4.4X10-8 ppm APPLICATIONS Input references are monitored for frequency offset and activity Industrial Automation DPLL holdover, free run and hitless reference switching can be Power Systems forced by the host processor or can be automatically controlled by an internal state machine Crystal Monitors IN1 Input Pre-Divider Priority Input Pre-Divider Priority IN2 Input Pre-Divider Priority IN3 OUT1 POS Divider OUT1 NEG Input DPLL/ APLL1 Selector DCO OUT2 POS (VCXO) Divider OUT2 NEG I2C Microprocessor Interface IN APLL1 POS OUT3 POS APLL2 Divider IN APLL1 NEG (VCXO) OUT3 NEG IN APLL2 POS IN APLL2 NEG JTAG OUT4 APLL OSCI Crystal Figure 1. Functional Block Diagram IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. TM IEEE 1588 is a trademark of its respective owner 1 May 5, 2014 IDT CONFIDENTIALIDIDT8T8V89317V89317 DAT DATASHEETASHEET 10G ETHERNET 10G ETHERNEPLL AND IEEE 1588 SYNTHESIZER FOR T PLL AND IEEE 1588 SYNTHESIZER FOR INDUSTRIINDUSTRIAL AAL AUTOMATIOUTOMATIONN AND POWER SYSTEMS AND POWER SYSTEMS DESCRIPTION The IDT8V89317 10G Ethernet PLL for Industrial Automation and The IDT8V89317 requires a 12.8 MHz master clock for its reference Power Systems is used to synchronize equipment with synchronization monitors and other digital circuitry. The frequency accuracy of the mas- sources using the Ethernet physical layer, or with a 1 PPS (1 Hz) GPS ter clock determines the frequency accuracy of the DPLL in Free-Run clock it can also be used by external IEEE 1588 clock recovery servos mode. The frequency stability of the master clock determines the fre- to synthesize IEEE 1588 clocks. The IDT8V89317 ultra-low jitter output quency stability of the DPLL in Free-Run mode and in Holdover mode. clocks can be used to directly synchronize 10GBASE-R Ethernet PHYs The master clock must be sufficiently stable to support the selected and XAUI or QSGMII devices. DPLL filtering bandwidth in particular, the 15 mHz bandwidth requires a very stable temperature compensated crystal oscillator (TCXO) or ove- The IDT8V89317 synchronization functions are provided by a Digital nized crystal oscillator (OCXO). Refer to the IDT application note Rec- PLL (DPLL) with an embedded clock synthesizer. The DPLL accepts ommended Crystal Oscillators for IDTs Network Synchronization WAN- three single ended reference inputs that can operate at 1PPS (1 Hz), 25 TM PLL for guidance. MHz, 125 MHz or 156.25 MHz. The references are continually moni- tored for loss of signal and for frequency offset per user programmed The DPLL can be configured with a filtering bandwidth of 15 mHz or thresholds. The active reference for the DPLL is determined by forced 1.2 Hz. The 15 mHz bandwidth can be used to lock the DPLL directly to selection or by automatic selection based on user programmed priorities a 1 pulse per second (PPS) reference. 1.2 Hz bandwidth can be used to and locking allowances and based on the reference monitors. lock to Ethernet connected synchronization sources operating at 25 MHz, 125 MHz or 156.25 MHz. The DPLL supports four primary operating modes: Free-Run, Locked, Holdover and Digitally Controlled Oscillator (DCO) Control. In The clock synthesized by the IDT8V89317 DPLL is passed through Free-Run mode the DPLL generates a clock based on the master clock two independent voltage controlled crystal oscillator (VCXO) based jitter alone. In Locked mode the DPLL filters reference clock jitter with the attenuating analog PLLs (APLLs). The APLLs drive independent divid- selected bandwidth. In Locked mode the long-term DPLL frequency ers that have differential outputs. The APLLs use external crystal reso- accuracy is the same as the long term frequency accuracy of the nators with resonant frequencies equal to the APLL base frequency selected input reference. In Holdover mode the DPLL uses frequency divided by 25. The output clocks generated by the APLLs exhibit jitter data acquired while in Locked mode to generate accurate frequencies below 0.30ps RMS over the integration range 10 kHz to 20 MHz. when input references are not available. In DCO Control Mode the DPLL The IDT8V89317 generates a 25 MHz single ended output that is control loop is opened and the DCO can be used by an algorithm (e.g. based on the free running 12.8 MHz master clock. The frequency accu- IEEE 1588 clock servo) running on an external processor to synthesize racy and the frequency stability of this 25 MHz clock are determined by clock signals. the master clock. Description 2 May 5, 2014 IDT CONFIDENTIAL