Low Power Wideband Fractional 8V97051L RF Synthesizer / PLL Datasheet Description Features The 8V97051L is a high-performance Wideband RF Synthesizer / Dual Differential Outputs PLL optimized for use as the local oscillator (LO) in Multi-Carrier, Output frequency range: 34.375MHz to 4400MHz (continuous Multi-mode FDD, and TDD Base Station radio card. It is offered in a range) compact 5 5, 32-VFQFN package with 50 differential RF output impedances for ease of integration into the receiver or transmitter RF Output Divide by 1, 2, 4, 8, 16, 32, 64 lineup. Open Drain Outputs (see Output Distribution Section) The 8V97051L Wideband RF Synthesizer / PLL offers a default Fractional-N synthesizer (also supports Integer-N mode) Fractional Mode with the option to use it with an Integer mode. It 16-bit integer and 12-bit fractional requires an external loop filter. (16-bit fractional when using the extended registers) The 8V97051L with integrated Voltage Controlled Oscillator (VCO) 3- or 4-wire SPI interface (compatible with 3.3V and 1.8V) supports output frequencies from 34.375MHz to 4400MHz, and Single 3.3V supply maintains superior phase noise and spurious performance. Logic compatibility: 1.8V RF OUT output drivers have independently programmable A:B Integrated high performance low dropout regulators (LDOs) for output power ranging from 4dBm to +7dBm. The RF OUT outputs excellent power supply noise rejection can be muted. The mute function is accessible via a SPI command or mute pin. Programmable output power level: -4dBm to +5dBm (up to +7 when using the extended registers) The operation of the 8V97051L is controlled by writing to registers Mute Function through a three-wire SPI interface. The device also has an additional option that allows users to read back values from registers by Ultra low PN for 1.1GHz LO: -143dBc/Hz at 1MHz Offset, (typical) configuring the MUX OUT pin as a SDO for the SPI interface. The Lock Detect Indicators SPI interface is compatible with 1.8V logic and tolerant to 3.3V. Input Reference frequency: 5MHz to 310MHz In multi-service base stations, very low noise oscillators are required Power Consumption: 380mW (typical) (RF OUT disabled) B to generate a large variety of frequencies to the mixers while maintaining excellent phase noise performance and low power. The 32-Lead, 5x5 VFQFN package 8V97051L offers a large tuning range capable of providing multi-band Automatic VCO band selection (Autocal feature) LO frequency synthesis in multi-mode base stations, thus limiting the use of multiple narrow band RF Synthesizers and reducing the BOM -40C to +85C ambient operating temperature complexity and cost. The device can operate over -40C to +85C Supports case temperature 105C operations industrial temperature range. Lead-free (RoHS 6) packaging Applications Wireless Infrastructure Test Equipment CATV Equipment Military and Aerospace Wireless LAN Clock Generation 2018 Integrated Device Technology, Inc. 1 August 7, 20188V97051L Datasheet Table of Contents Description 1 Applications 1 Features 1 8V97051L Block Diagram .6 Pin Assignment .6 Pin Description and Characteristic Tables 7 Table 1. Pin Description .7 Table 2. Pin Characteristics 8 Table 3. Supply Pins and Associated Current Return Paths .8 Principles of Operation .9 Synthesizer Programming 9 Reference Input Stage .9 Reference Doubler 9 Table 4A. Lock Detect Precision (LDP) .9 Feedback Divider .9 Figure 1. RF Feedback N Divider .10 Table 4B. Fractional Spurs Due to the Quantization Noise .10 Phase and Frequency Detector (PFD) and Charge Pump 11 Figure 2. Simplified PFD Circuit using D-type Flip-flop 11 PFD Frequency 11 External Loop Filter .11 Phase Detector Polarity .11 Charge Pump High-Impedance .11 Integrated Low Noise VCO .11 Output Distribution Section .12 Figure 3. Output Clock Distribution 12 Figure 4. Output Stage .12 Output Matching .12 Figure 5. Broadband Matching Termination .12 Figure 6. Optimal Matching Termination 12 Band Selection Disable 12 Phase Adjust 13 Phase Resync .13 Figure 7. 12-bit Counter for Fast Lock and Phase Resync 13 Fast Lock Function .13 Figure 8. Example of Fast Lock Mode Loop Filter Topology 14 RF Output Power 14 MUX OUT 14 Table 4C. MUX OUT Pin Configuration 14 Power-Down Mode .14 Default Power-Up Conditions .14 Program Modes 14 Table 4D. Control Bits Configuration 14 2018 Integrated Device Technology, Inc. 2 August 7, 2018