DATASHEET TM Programmable Timing Control Hub for Next Gen TM ICS932S208 P4 Processor Features/Benefits: Recommended Application: Supports tight ppm accuracy clocks for Serial-ATA CK409B clock, Intel Yellow Cover part, Server Applications Supports spread spectrum modulation, 0 to -0.5% down spread and +/- 0.25% center spread Output Features: 4 - 0.7V current-mode differential CPU pairs Supports CPU clks up to 400MHz in test mode 1 - 0.7V current-mode differential SRC pair Uses external 14.318MHz crystal 7 - PCI (33MHz) 3 - PCICLK F, (33MHz) free-running Pin Configuration 1 - USB, 48MHz REF0 1 56 FS B 1 - DOT, 48MHz REF1 2 55 VDDA 2 - REF, 14.318MHz VDDREF 3 54 GNDA 4 - 3V66, 66.66MHz X1 4 53 GND 1 - VCH/3V66, selectable 48MHz or 66MHz X2 5 52 IREF GND 6 51 FS A Key Specifications: PCICLK F0 7 50 CPUCLKT3 CPU/SRC outputs cycle-cycle jitter < 125ps PCICLK F1 8 49 CPUCLKC3 3V66 outputs cycle-cycle jitter < 250ps PCICLK F2 9 48 VDDCPU PCI outputs cycle-cycle jitter < 250ps VDDPCI 10 47 CPUCLKT2 CPU outputs skew: < 100ps GND 11 46 CPUCLKC2 +/- 300ppm frequency accuracy on CPU & SRC clocks PCICLK0 12 45 GND PCICLK1 13 44 CPUCLKT1 Functionality PCICLK2 14 43 CPUCLKC1 CPU SRC 3V66 PCI REF USB/DOT PCICLK3 15 42 VDDCPU B6b5 FS A FS B MHz MHz MHz MHz MHz MHz VDDPCI 16 41 CPUCLKT0 0 0 100 100/200 66.66 33.33 14.318 48.00 GND 17 40 CPUCLKC0 0 MID Ref/N Ref/N Ref/N Ref/N Ref/N Ref/N 0 1 2 3 4 5 0 1 200 100/200 66.66 33.33 14.318 48.00 PCICLK4 18 39 GND 0 1 0 133 100/200 66.66 33.33 14.318 48.00 PCICLK5 19 38 SRCCLKT 1 1 166 100/200 66.66 33.33 14.318 48.00 PCICLK6 20 37 SRCCLKC 1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 200 100/200 66.66 33.33 14.318 48.00 PD 21 36 VDD 0 1 400 100/200 66.66 33.33 14.318 48.00 1 3V66 0 22 35 Vtt PWRGD 1 0 266 100/200 66.66 33.33 14.318 48.00 1 1 333 100/200 66.66 33.33 14.318 48.00 3V66 1 23 34 VDD48 VDD3V66 24 33 GND GND 25 32 48MHz DOT 3V66 2 26 31 48MHz USB 3V66 3 27 30 SDATA SCLK 28 29 3V66 4/VCH 56-pin SSOP & TSSOP TM TM IDT Programmable Timing Control Hub for Next Gen P4 Processor 0743H03/15/13 1 ICS932S208ICS932S208 TM TM Programmable Timing Control Hub for Next Gen P4 Processor Pin Description PIN PIN NAME PIN TYPE DESCRIPTION 1 REF0 OUT 14.318 MHz reference clock. 2 REF1 OUT 14.318 MHz reference clock. 3 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 4X1 IN Crystal input, Nominally 14.318MHz. 5 X2 OUT Crystal output, Nominally 14.318MHz 6 GND PWR Ground pin. 7 PCICLK F0 OUT Free running PCI clock not affected by PCI STOP . 8 PCICLK F1 OUT Free running PCI clock not affected by PCI STOP . 9 PCICLK F2 OUT Free running PCI clock not affected by PCI STOP . 10 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 11 GND PWR Ground pin. 12 PCICLK0 OUT PCI clock output. 13 PCICLK1 OUT PCI clock output. 14 PCICLK2 OUT PCI clock output. 15 PCICLK3 OUT PCI clock output. 16 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 17 GND PWR Ground pin. 18 PCICLK4 OUT PCI clock output. 19 PCICLK5 OUT PCI clock output. 20 PCICLK6 OUT PCI clock output. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the 21 PD IN crystal are stopped. The latency of the power down will not be greater than 1.8ms. Internal pull-up of 150K nominal. 22 3V66 0 OUT 3.3V 66.66MHz clock output 23 3V66 1 OUT 3.3V 66.66MHz clock output 24 VDD3V66 PWR Power pin for the 3V66 clocks. 25 GND PWR Ground pin. 26 3V66 2 OUT 3.3V 66.66MHz clock output 27 3V66 3 OUT 3.3V 66.66MHz clock output 28 SCLK IN Clock pin of I2C circuitry 5V tolerant TM TM IDT Programmable Timing Control Hub for Next Gen P4 Processor 0743H03/15/13 2