Integrated ICS932S401 Circuit Systems, Inc. Programmable Timing Control Hub for Intel-based Servers Recommended Application: Key Specifications: CK410B clock for Intel-based servers CPU cycle-cycle jitter: < 50ps SRC cycle-cycle jitter: < 125ps Output Features: PCI cycle-cycle jitter: < 500ps 4 - 0.7V current-mode differential CPU pairs CPU output skew: < 50ps 5 - 0.7V current-mode differential SRC pair SRC output skew: < 250ps 4 - PCI (33MHz) 300ppm frequency accuracy on all outputs except 3 - PCICLK F, (33MHz) free-running 48MHz 1 - 48MHz 100ppm frequency accuracy on 48MHz 2 - REF, 14.318MHz Features/Benefits: Supports spread spectrum modulation, 0 to -0.5% down spread Uses external 14.318MHz crystal and external load capacitors for low ppm synthesis error CPU clocks independent of SRC/PCI clocks D2/D3 SMBus address 932S401 Functionality Pin Configuration CPU SRC PCI REF USB 1 1 2 VDDPCI 1 56 FS C/TEST SEL FS C FS B FS A MHz MHz MHz MHz MHz GNDPCI 2 55 REF0 0 0 0 266.67 100.00 33.33 14.318 48.000 0 0 1 133.33 100.00 33.33 14.318 48.000 PCICLK0 3 54 REF1 0 1 0 200.00 100.00 33.33 14.318 48.000 PCICLK1 4 53 VDDREF 0 1 1 166.67 100.00 33.33 14.318 48.000 1 0 0 333.33 100.00 33.33 14.318 48.000 PCICLK2 5 52 X1 1 0 1 100.00 100.00 33.33 14.318 48.000 PCICLK3 6 51 X2 1 1 0 400.00 100.00 33.33 14.318 48.000 GNDPCI 7 50 GNDREF 11 1 Reserved VDDPCI 8 49 FS B/TEST MODE 1. FS B and FS C are three-level inputs. Please see V and V specifications in IL FS IH FS the Input/Supply/Common Output Parameters Table for correct values. PCICLK F0 9 48 FS A Also refer to the Test Clarification Table. PCICLK F1 10 47 VDDCPU 2. FS A is a low-threshold input. Please see the V and V IL FS IH FS PCICLK F2 11 46 CPUCLKT0 specifications in the Input/Supply/Common Output Parameters Table for correct values. VDD48 12 45 CPUCLKC0 48MHz 13 44 VDDCPU GND4814 43CPUCLKT1 VDDSRC 15 42 CPUCLKC1 SRCCLKT0 16 41 GNDCPU SRCCLKC0 17 40 CPUCLKT2 SRCCLKC1 18 39 CPUCLKC2 SRCCLKT1 19 38 VDDCPU GNDSRC 20 37 CPUCLKT3 SRCCLKT2 21 36 CPUCLKC3 SRCCLKC2 22 35 VDDA SRCCLKC3 23 34 GNDA SRCCLKT3 24 33 IREF VDDSRC 25 32 NC SRCCLKT4 26 31 Vtt PwrGd /PD SRCCLKC4 27 30 SDATA VDDSRC 28 29 SCLK 56-pin SSOP & TSSOP 0921G08/24/09 ICS932S401Integrated ICS932S401 Circuit Systems, Inc. Pin Description Pin PIN NAME PIN TYPE DESCRIPTION 1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GNDPCI PWR Ground pin for the PCI outputs 3 PCICLK0 OUT PCI clock output. 4 PCICLK1 OUT PCI clock output. 5 PCICLK2 OUT PCI clock output. 6 PCICLK3 OUT PCI clock output. 7 GNDPCI PWR Ground pin for the PCI outputs 8 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 9 PCICLK F0 OUT Free running PCI clock not affected by PCI STOP . 10 PCICLK F1 OUT Free running PCI clock not affected by PCI STOP . 11 PCICLK F2 OUT Free running PCI clock not affected by PCI STOP . 12 VDD48 PWR Power pin for the 48MHz output.3.3V 13 48MHz OUT 48MHz clock output. 14 GND48 PWR Ground pin for the 48MHz outputs 15 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 16 SRCCLKT0 OUT True clock of differential SRC clock pair. 17 SRCCLKC0 OUT Complement clock of differential SRC clock pair. 18 SRCCLKC1 OUT Complement clock of differential SRC clock pair. 19 SRCCLKT1 OUT True clock of differential SRC clock pair. 20 GNDSRC PWR Ground pin for the SRC outputs 21 SRCCLKT2 OUT True clock of differential SRC clock pair. 22 SRCCLKC2 OUT Complement clock of differential SRC clock pair. 23 SRCCLKC3 OUT Complement clock of differential SRC clock pair. 24 SRCCLKT3 OUT True clock of differential SRC clock pair. 25 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 26 SRCCLKT4 OUT True clock of differential SRC clock pair. 27 SRCCLKC4 OUT Complement clock of differential SRC clock pair. 28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 0921G08/24/09 2