932S421BGLFT Renesas

DATASHEET PCIe Gen2 and QPI Clock for Intel-Based Servers ICS932S421B Key Specifications: Recommended Application: PCIe Gen 2 compliant SRC outputs PCIe Gen 2 & QPI compliant CK410B+ clock for Intel-based servers QPI & FBD 2 compliant CPU clocks CPU cycle-cycle jitter: < 50ps Output Features: SRC cycle-cycle jitter: < 125ps 4 - 0.7V current-mode differential CPU pairs PCI cycle-cycle jitter: < 500ps 5 - 0.7V current-mode differential SRC pair CPU output skew: < 50ps 4 - PCI (33MHz) SRC output skew: < 250ps 3 - PCICLK F, (33MHz) free-running 100ppm frequency accuracy on all outputs 1 - 48MHz 2 - REF, 14.318MHz Functionality CPU SRC PCI REF USB 1 1 2 FS C FS B FS A MHz MHz MHz MHz MHz Features/Benefits: 0 0 0 266.67 Supports spread spectrum modulation, 0 to -0.5% 0 0 1 133.33 down spread 0 1 0 200.00 0 1 1 166.67 100.00 33.33 14.32 48.00 Uses external 14.318MHz crystal and external load 1 0 0 333.33 capacitors for low ppm synthesis error 1 0 1 100.00 CPU clocks independent of SRC/PCI clocks 1 1 0 400.00 11 1 Reserved D2/D3 SMBus address 1. FS B and FS C are three-level inputs. Please see V and V specifications in IL FS IH FS the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS A is a low-threshold input. Please see the V and V IL FS IH FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Pin Configuration VDDPCI 1 56 FS C/TEST SEL GNDPCI 2 55 REF0 PCICLK0 3 54 REF1 PCICLK1 4 53 VDDREF PCICLK2 5 52 X1 PCICLK3 6 51 X2 GNDPCI 7 50 GNDREF VDDPCI 8 49 FS B/TEST MODE PCICLK F0 9 48 FS A PCICLK F1 10 47 VDDCPU PCICLK F2 11 46 CPUCLKT0 VDD48 12 45 CPUCLKC0 48MHz 13 44 VDDCPU GND48 14 43 CPUCLKT1 VDDSRC 15 42 CPUCLKC1 SRCCLKT0 16 41 GNDCPU SRCCLKC0 17 40 CPUCLKT2 SRCCLKC1 18 39 CPUCLKC2 SRCCLKT1 19 38 VDDCPU GNDSRC 20 37 CPUCLKT3 SRCCLKT2 21 36 CPUCLKC3 SRCCLKC2 22 35 VDDA SRCCLKC3 23 34 GNDA SRCCLKT3 24 33 IREF VDDSRC 25 32 NC SRCCLKT4 26 31 Vtt PwrGd /PD SRCCLKC4 27 30 SDATA VDDSRC 28 29 SCLK 56-pin SSOP & TSSOP TM IDT PCIe Gen2 and QPI Clock for Intel-Based Servers 1340G01/26/10 1 ICS932S421ICS932S421B PCIe Gen2 and QPI Clock for Intel-Based Servers Pin Description Pin PIN NAME PIN TYPE DESCRIPTION 1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GNDPCI PWR Ground pin for the PCI outputs 3 PCICLK0 OUT PCI clock output. 4 PCICLK1 OUT PCI clock output. 5 PCICLK2 OUT PCI clock output. 6 PCICLK3 OUT PCI clock output. 7 GNDPCI PWR Ground pin for the PCI outputs 8 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 9 PCICLK F0 OUT Free running PCI clock not affected by PCI STOP . 10 PCICLK F1 OUT Free running PCI clock not affected by PCI STOP . 11 PCICLK F2 OUT Free running PCI clock not affected by PCI STOP . 12 VDD48 PWR Power pin for the 48MHz output.3.3V 13 48MHz OUT 48MHz clock output. 14 GND48 PWR Ground pin for the 48MHz outputs 15 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 16 SRCCLKT0 OUT True clock of differential SRC clock pair. 17 SRCCLKC0 OUT Complement clock of differential SRC clock pair. 18 SRCCLKC1 OUT Complement clock of differential push-pull SRC clock pair. 19 SRCCLKT1 OUT True clock of differential SRC clock pair. 20 GNDSRC PWR Ground pin for the SRC outputs 21 SRCCLKT2 OUT True clock of differential SRC clock pair. 22 SRCCLKC2 OUT Complement clock of differential SRC clock pair. 23 SRCCLKC3 OUT Complement clock of differential SRC clock pair. 24 SRCCLKT3 OUT True clock of differential SRC clock pair. 25 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 26 SRCCLKT4 OUT True clock of differential SRC clock pair. 27 SRCCLKC4 OUT Complement clock of differential SRC clock pair. 28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal TM IDT PCIe Gen2 and QPI Clock for Intel-Based Servers 1340G01/26/10 2