DATASHEET RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS 932S890C General Description Features/Benefits The 932S890C is a main clock synthesizer chip for Spread Spectrum EMI reduction SR5690/SR5670 AMD Servers. An SMBus interface allows Outputs may be disabled via SMBus saves power full control of the device. External crystal load capacitors maximum frequency accuracy Recommended Application Key Specifications SR5690/SR5670 AMD-based Servers CPU output cycle-to-cycle jitter <100ps Output Features SRC output cycle-to-cycle jitter <125ps Low power differential outputs with integrated series 48MHz output cycle-to-cycle jitter <130ps resistors for Zo=50ohm systems SIO output cycle-to-cycle jitter <150ps 4 -Differential 200MHz CPU pairs SRC output phase jitter <3.1ps rms (PCIe Gen2) 2 - Differential 100MHz HT3 pairs +/- 50ppm frequency accuracy on all clocks, assuming 14 - Differential PCIe Gen2 SRC pairs REF is trimmed to 0 ppm) 1 - Differential non-spread SATA clock 2 - 48MHz USB clocks (180 degrees out of phase for EMI Table 1: 932S890 Functionality reduction) CPU HTT SRC REF USB DOT SATA SIO 2 - SIO clocks (selectable 48MHz or 24MHz). 180 MHz MHz MHz MHz MHz MHz 200.00 100.00 100.00 100.00 14.318 24/48 48.00 96.00 degrees out of phase for EMI reduction 2 - 14.318MHz REF clock outputs Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDDSATA 3.3 1 54 SRC6T LPRS SATAC LPRS 2 53 SRC6C LPRS SATAT LPRS 3 52 SRC5T LPRS GNDSATA 4 51 SRC5C LPRS VDDSRC 3.3 CPUKG0C LPRS 5 50 GNDSRC CPUKG0T LPRS 6 49 CPUKG1C LPRS 48 SRC4T LPRS 7 CPUKG1T LPRS 47 SRC4C LPRS 8 VDDCPU 3.3 46 SRC3T LPRS 9 932S890C GNDCPU 10 45 SRC3C LPRS CPUKG2C LPRS 11 44 SRC2T LPRS CPUKG2T LPRS 12 43 SRC2C LPRS CPUKG3C LPRS 13 42 GNDSRC CPUKG3T LPRS 14 41 VDDSRC 3.3 15 40 SRC1T LPRS RESTORE HTT0C LPRS 16 39 SRC1C LPRS HTT0T LPRS 17 38 SRC0T LPRS GNDHTT 18 37 SRC0C LPRS 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 * Indicates that pin has 120Kohm internal pullup resistor. IDT RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS 1 932S890C REV D 052011 VDDHTT 3.3 SRC13T LPRS HTT1C LPRS SRC13C LPRS HTT1T LPRS SRC12T LPRS SMBCLK SRC12C LPRS SMBDAT VDDSRC 3.3 X1 GNDSRC X2 SRC11T LPRS VDDREF 3.3 SRC11C LPRS REF0 SRC10T LPRS REF1 SRC10C LPRS GNDREF SRC9T LPRS GND48 SRC9C LPRS 48MHz 0 GNDSRC 48MHz 1 VDDSRC 3.3 VDD48 3.3 SRC8T LPRS SIO 0 1.8/SIO SE SRC8C LPRS SIO 1 1.8 SRC7T LPRS GNDSIO SRC7C LPRS932S890C RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS Pin Descriptions PIN PIN NAME PIN TYPE DESCRIPTION 1 VDDSATA 3.3 PWR Power supply for SATA core logic, nominal 3.3V Complement clock of low power differential SATA clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm 2 SATAC LPRS OUT series resistor needed) True clock of low power differential SATA clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series 3SATAT LPRS OUT resistor needed) 4 GNDSATA GND Ground pin for the SATA output Complementary signal of low-power differential push-pull AMDGreyhoun clock with integrated series resistor. 5 CPUKG0C LPRS OUT (no 33 ohm series resistor needed and no 50 ohm pull down resistor needed) True signal of low-power differential push-pull AMDGreyhoun CPU clock with integrated series resistor(no 33 6CPUKG0T LPRS OUT ohm series resistor needed and no 50 ohm pull down resistor needed) Complementary signal of low-power differential push-pull AMDGreyhoun CPU clock with integrated series 7 CPUKG1C LPRS OUT resistor. (no 33 ohm series resistor needed and no 50 ohm pull down resistor needed) True signal of low-power differential push-pull AMDGreyhoun CPU clock with integrated series resistor(no 33 8CPUKG1T LPRS OUT ohm series resistor needed and no 50 ohm pull down resistor needed) 9 VDDCPU 3.3 PWR Supply for CPU core and outputs, 3.3V nominal 10 GNDCPU GND Ground pin for the CPU outputs Complementary signal of low-power differential push-pull AMDGreyhoun CPU clock with integrated series 11 CPUKG2C LPRS OUT resistor. (no 33 ohm series resistor needed and no 50 ohm pull down resistor needed) True signal of low-power differential push-pull AMDGreyhoun CPU clock with integrated series resistor(no 33 12 CPUKG2T LPRS OUT ohm series resistor needed and no 50 ohm pull down resistor needed) Complementary signal of low-power differential push-pull AMDGreyhoun CPU clock with integrated series 13 CPUKG3C LPRS OUT resistor. (no 33 ohm series resistor needed and no 50 ohm pull down resistor needed) True signal of low-power differential push-pull AMDGreyhoun CPU clock with integrated series resistor(no 33 14 CPUKG3T LPRS OUT ohm series resistor needed and no 50 ohm pull down resistor needed) Open Drain I/O. As an input it restores the PLL s to power up default state. As an output, this signal is driven low when the internal watchdog hardware timer expires. It is cleared when the internal watchdog hardware timer is 15 RESTORE I/O reset or disabled. The input is falling edge triggered. 0 = Restore Settings, 1 = normal operation. Complementary signal of low-power differential push-pull Hypertransport 3 clock with integrated series resistor. 16 HTT0C LPRS OUT (no 50 ohm shunt resistor to GND and no 33 ohm series resistor needed) True signal of low-power differential push-pull Hypertransport 3 clock with integrated series resistor. (no 50 ohm 17 HTT0T LPRS OUT shunt resistor to GND and no 33 ohm series resistor needed) 18 GNDHTT PWR Ground pin for the HTT outputs 19 VDDHTT 3.3 PWR Supply for HTT clocks, nominal 3.3V. Complementary signal of low-power differential push-pull Hypertransport 3 clock with integrated series resistor. 20 HTT1C LPRS OUT (no 50 ohm shunt resistor to GND and no 33 ohm series resistor needed) True signal of low-power differential push-pull Hypertransport 3 clock with integrated series resistor. (no 50 ohm 21 HTT1T LPRS OUT shunt resistor to GND and no 33 ohm series resistor needed) 22 SMBCLK IN Clock pin of SMBus circuitry, 5V tolerant. 23 SMBDAT I/O Data pin for SMBus circuitry, 5V tolerant. 24 X1 IN Crystal input, nominally 14.318MHz 25 X2 OUT Crystal output, nominally 14.318MHz 26 VDDREF 3.3 PWR Ref, XTAL power supply, nominal 3.3V 27 REF0 OUT 14.318 MHz reference clock, 3.3V 28 REF1 OUT 14.318 MHz reference clock, 3.3V 29 GNDREF GND Ground pin for the REF outputs. 30 GND48 GND Ground pin for the 48MHz outputs 31 48MHz 0 OUT 48MHz clock output. 32 48MHz 1 OUT 48MHz clock output. (180 degrees out of phase with 48MHz 0) 33 VDD48 3.3 PWR Power pin for the 48MHz and SIO outputs and core. 3.3V Selectable 48MHz or 24MHz output/SIO Select Latched Input 34 SIO 0 1.8/SIO SEL I/O 0 = 24MHz, 1 = 48MHz. Selectable 48MHz or 24MHz output. (180 out of phase with SIO 0. Selected by SIO latched input. 35 SIO 1 1.8 OUT 0 = 24MHz, 1 = 48MHz. 36 GNDSIO GND Ground pin for the SIO outputs IDT RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS 2 932S890C REV D 052011