NS SRC(1:0) DATASHEET PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 932SQ420D General Description Features/Benefits The 932SQ420D is a main clock synthesizer for 0.5% down spread capable on CPU/SRC/PCI Romley-generation Intel based server platforms. The outputs/Lower EMI 932SQ420D is driven with a 25 MHz crystal for maximum 64-pin TSSOP and MLF packages/Space Savings performance. It generates CPU outputs of 100 or 133.33 MHz. Key Specifications Cycle to cycle jitter: CPU/SRC/NS SRC/NS SAS < Recommended Application 50ps. CK420BQ Phase jitter: PCIe Gen2 < 3ps rms, Gen3 < 1ps rms Phase jitter: QPI 9.6GB/s < 0.2ps rms Output Features Phase jitter: NS-SAS < 0.4ps rms using raw phase data 4 - HCSL CPU outputs Phase jitter: NS-SAS < 1.3ps rms using Clk Jit Tool 1.6.3 4 - HCSL Non-Spread SAS/SRC outputs 3 - HCSL SRC outputs 1 - HCSL DOT96 output 1 - 3.3V 48M output 5 - 3.3V PCI outputs 1- 3.3V REF output Block Diagram CPU(3:0) X1 25 CPU SRC PCI SRC(2:0) X2 PLL (SS) PCI(4:0) /3 NS SAS(1:0) Low Drift non-SS PLL <500ps LTJ DOT96 Non-SS PLL 48M /2 14.31818MHz REF14M Non-SS PLL Test Sel Test Mode 100M 133M Logic CKPWRGD /PD SMBDAT SMBCLK IREF IDT PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 1 932SQ420D REV J 010715932SQ420D PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS Pin Configuration - 64TSSOP SMBCLK 1 64 SMBDAT GND14 2 63 VDDCPU AVDD14 3 62 CPU3T VDD14 4 61 CPU3C v REF14 3x/TEST SEL 5 60 CPU2T GND14 6 59 CPU2C GNDXTAL 7 58 GNDCPU X1 25 8 57 VDDCPU X2 25 9 56 CPU1T VDDXTAL10 55CPU1C GNDPCI 11 54 CPU0T VDDPCI 12 53 CPU0C PCI4 2x 13 52 GNDNS PCI3 2x 14 51 AVDD NS SAS PCI2 2x 15 50 NS SAS1T PCI1 2x 16 49 NS SAS1C PCI0 2x 17 48 NS SAS0T GNDPCI 18 47 NS SAS0C VDDPCI 19 46 GNDNS VDD4820 45VDDNS 48M 2x/100M 133M 21 44 NS SRC1T GND4822 43NS SRC1C GND9623 42NS SRC0T DOT96T 24 41 NS SRC0C DOT96C 25 40 IREF AVDD96 26 39 GNDSRC TEST MODE 27 38 AVDD SRC CKPWRGD /PD 28 37 VDDSRC VDDSRC 29 36 SRC2T SRC0T 30 35 SRC2C SRC0C 31 34 SRC1T GNDSRC 32 33 SRC1C 64-TSSOP Note: Pins with prefix have internal 120K pullup Pins with v prefix have internal 120K pulldown Spread Spectrum Control 932SQ420 Power Down Functionality SS Enable CPU, SRC & Differential Single-ended Single ended CKPWRGD /PD Outputs Outputs Outputs w/Latch (B1b0) PCI 1 2 1HI-Z Low Low 0OFF 0 Running 1ON 1. Hi-Z on the differential outputs will result in both True and Complement being low due to the termination network 2. These outputs are Hi-Z after VDD is applied and before the first Power Group Pin Numbers assertion of CKPWRGD . MLF TSSOP Description VDD GND VDD GND 57 56 3 2 14MHz PLL Analog 58 60 4 6 REF14M Output and Logic 64 61 10 7 25MHz XTAL 2, 9 1, 8 12, 19 11, 18 PCI Outputs and Logic 10 12 20 22 48MHz Output and Logic 16 13 26 23 96MHz PLL Analog, Output and Logic 19, 27 22 29, 37 32 SRC Outputs and Logic 28 29 38 39 SRC PLL Analog Non-Spreading Differential Outputs & Logic 35 36 45 46 41 42 51 52 NS-SAS/SRC PLL Analog 47, 53 48 57,63 58 CPU Outputs and Logic IDT PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 2 932SQ420D REV J 010715 932SQ420