ICS954101 Integrated ICS954101 Circuit Systems, Inc. Programmable Timing Control Hub for Desktop P4 Systems Recommended Application: Features/Benefits: CK410 clock, Intel Yellow Cover part Supports tight ppm accuracy clocks for Serial-ATA and PCI-Express Output Features: Supports spread spectrum modulation, 0 to -0.5% down spread 2 - 0.7V current-mode differential CPU pairs 6 - 0.7V current-mode differential SRC pair for SATA and Supports CPU clks up to 400MHz PCI-E Uses external 14.318MHz crystal, external crystal load 1 - 0.7V current-mode differential CPU/SRC selectable caps are required for frequency tuning pair Supports undriven differential CPU, SRC pair in PD 6 - PCI (33MHz) for power management. 3 - PCICLK F, (33MHz) free-running 1 - USB, 48MHz 1 - DOT, 96MHz, 0.7V current differential pair 1 - REF, 14.318MHz Key Specifications: CPU outputs cycle-cycle jitter < 85ps SRC output cycle-cycle jitter <125ps PCI outputs cycle-cycle jitter < 500ps +/- 300ppm frequency accuracy on CPU & SRC clocks Functionality Pin Configuration CPU SRC PCI REF USB DOT 1 2 2 VDDPCI 1 56 PCICLK2 FS C FS B FS A MHz MHz MHz MHz MHz MHz GND 2 55 PCICLK1 0 0 0 266.66 100.00 33.33 14.318 48.00 96.00 0 0 1 133.33 100.00 33.33 14.318 48.00 96.00 PCICLK3 3 54 PCICLK0 0 1 0 200.00 100.00 33.33 14.318 48.00 96.00 PCICLK4 4 53 FS C/TEST SEL 0 1 1 166.66 100.00 33.33 14.318 48.00 96.00 PCICLK5 5 52 REFOUT 1 0 0 333.33 100.00 33.33 14.318 48.00 96.00 0 1 100.00 100.00 33.33 14.318 48.00 96.00 GND 6 51 GND 1 1 1 0 400.00 100.00 33.33 14.318 48.00 96.00 VDDPCI 7 50 X1 1 1 1 RESERVED 14.318 48.00 96.00 ITP EN/PCICLK F0 8 49 X2 PCICLK F1 9 48 VDDREF 1. FS C is a three-level input. Please see V and V specifications in IL FS IH FS the Input/Supply/Common Output Parameters Table for correct values. PCICLK F210 47SDATA Also refer to the Test Clarification Table. VDD4811 46SCLK 2. FS B and FS A are low-threshold inputs. Please see the V and V IL FS IH FS USB 48MHz 12 45 GND specifications in the Input/Supply/Common Output Parameters Table for correct values. GND 13 44 CPUCLKT0 DOTT 96MHz 14 43 CPUCLKC0 DOTC 96MHz 15 42 VDDCPU FS B/TEST MODE 16 41 CPUCLKT1 Vtt PwrGd /PD 17 40 CPUCLKC1 FS A 410 18 39 IREF SRCCLKT1 19 38 GNDA SRCCLKC1 20 37 VDDA VDDSRC 21 36 CPUCLKT2 ITP/SRCCLKT 7 SRCCLKT2 22 35 CPUCLKC2 ITP/SRCCLKC 7 SRCCLKC2 23 34 VDDSRC SRCCLKT3 24 33 SRCCLKT6 SRCCLKC3 25 32 SRCCLKC6 SRCCLKT4 SATA 26 31 SRCCLKT5 SRCCLKC4 SATA 27 30 SRCCLKC5 VDDSRC 28 29 GND 56-pin SSOP & TSSOP 0815G12/02/08Integrated ICS954101 Circuit Systems, Inc. Pin Description Pin PIN NAME PIN TYPE DESCRIPTION 1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GND PWR Ground pin. 3 PCICLK3 OUT PCI clock output. 4 PCICLK4 OUT PCI clock output. 5 PCICLK5 OUT PCI clock output. 6 GND PWR Ground pin. 7 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI STOP . ITP EN: latched input to select pin functionality 8 ITP EN/PCICLK F0 I/O 1 = CPU ITP pair 0 = SRC pair 9 PCICLK F1 OUT Free running PCI clock not affected by PCI STOP . 10 PCICLK F2 OUT Free running PCI clock not affected by PCI STOP . 11 VDD48 PWR Power pin for the 48MHz output.3.3V 12 USB 48MHz OUT 48.00MHz USB clock 13 GND PWR Ground pin. 14 DOTT 96MHz OUT True clock of differential pair for 96.00MHz DOT clock. 15 DOTC 96MHz OUT Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil FS and Vih FS values. TEST MODE is a real time 16 FS B/TEST MODE IN input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. Vtt PwrGd is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin 17 Vtt PwrGd /PD IN used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 3.3V tolerant low threshold input for CPU frequency selection. This pin 18 FS A 410 IN requires CK410 FSA. Refer to input electrical characteristics for Vil FS and Vih FS threshold values. 19 SRCCLKT1 OUT True clock of differential SRC clock pair. 20 SRCCLKC1 OUT Complement clock of differential SRC clock pair. 21 VDDSRC PWR Supply for SRC clocks, 3.3V nominal pair. 22 SRCCLKT2 OUT True clock of differential SRC clock 23 SRCCLKC2 OUT Complement clock of differential SRC clock pair. 24 SRCCLKT3 OUT True clock of differential SRC clock pair. 25 SRCCLKC3 OUT Complement clock of differential SRC clock pair. 26 SRCCLKT4 SATA OUT True clock of differential SRC/SATA pair. 27 SRCCLKC4 SATA OUT Complement clock of differential SRC/SATA pair. 28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 0815G12/02/08 2