954119 Datasheet Programmable Timing Control Hub for Next Gen P4 processor Recommended Application: Features/Benefits: CK410 compliant clock Programmable output frequencies Programmable output skew. Output Features: Programmable spread percentage for EMI control. 2 - 0.7V current-mode differential CPU pairs Programmable watch dog safe frequency. 1 - 0.7V current-mode differential SRC pair Supports tight ppm accuracy clocks for Serial-ATA 6 - PCI (33MHz) Supports spread spectrum modulation, 0 to -0.5% 3 - PCICLK F, (33MHz) free-running down spread, 0.25% center spread, and 0.3% center spread 1 - USB, 48MHz 1 - 24/48 MHz Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning 1 - DOT, 96MHz, 0.7V current differential pair 2 - REF, 14.318MHz Supports undriven differential CPU, SRC pair in PD for power management. 5 - PCI-Express 0.7V current differential pairs Key Specifications: CPU/SRC outputs cycle-cycle jitter < 85ps PCI outputs cycle-cycle jitter < 250ps +/- 300ppm frequency accuracy on CPU & SRC clocks Functionality Pin Configuration Bit2 Bit1 Bit0 CPU PCIEX SRC PCI GND 1 56 VDDPCI Bit4 Bit3 FSLC FSLB FSLA MHz MHz MHz MHz PCICLK3 2 55 PCICLK2 266.66 100.00 100.00 33.33 0000 0 PCICLK4 3 54 PCICLK1 0000 1 133.33 100.00 100.00 33.33 PCICLK5 4 53 PCICLK0 0001 0 200.00 100.00 100.00 33.33 GND 5 52 Reset 166.66 100.00 100.00 33.33 0001 1 0010 0 333.33 100.00 100.00 33.33 VDDPCI 6 51 REF0/FS C L 100.00 100.00 100.00 33.33 0010 1 PCICLK F0 7 50 REF1 0011 0 400.00 100.00 100.00 33.33 FS A/PCICLK F1 8 49 GND L 200.00 100.00 100.00 33.33 0011 1 FS B/PCICLK F2 9 48 X1 L 266.66 133.33 133.33 33.33 0100 0 VDD4810 47X2 133.33 133.33 133.33 33.33 0100 1 **SEL24 48 /24 48MHz 11 46 VDDREF 0101 0 200.00 133.33 133.33 33.33 USB 48MHz 12 45 SCLK 0101 1 166.66 125.00 125.00 33.33 333.33 125.00 125.00 33.33 0110 0 GND 13 44 SDATA 100.00 133.33 133.33 33.33 0110 1 DOTT 96MHz 14 43 CPUCLKT0 400.00 133.33 133.33 33.33 0111 0 DOTC 96MHz 15 42 CPUCLKC0 0111 1 200.00 133.33 133.33 33.33 Vtt PwrGd /PD 16 41 VDDCPU 1000 0 269.33 101.00 101.00 33.67 PCIEXT017 40CPUCLKT1 1000 1 134.66 101.00 101.00 33.67 PCIEXC018 39CPUCLKC1 1001 0 202.00 101.00 101.00 33.67 1001 1 VDDPCIEX 19 38 GND 168.33 101.00 101.00 33.67 1010 0 274.66 103.00 103.00 34.33 GND 20 37 IREF 1010 1 137.33 103.00 103.00 34.33 PCIEXT121 36GNDA 1011 0 206.00 103.00 103.00 34.33 PCIEXC122 35VDDA 1011 1 171.66 103.00 103.00 34.33 PCIEXT223 34VDDPCIEX 1100 0 279.99 105.00 105.00 35.00 PCIEXC2 24 33 PCIEXT4 1100 1 140.00 105.00 105.00 35.00 1101 0 GND 25 32 PCIEXC4 210.00 105.00 105.00 35.00 1101 1 174.99 105.00 105.00 35.00 SRCCLKT 26 31 PCIEXT3 1110 0 287.99 108.00 108.00 36.00 SRCCLKC 27 30 PCIEXC3 1110 1 144.00 108.00 108.00 36.00 VDDSRC 28 29 GND 1111 0 216.00 108.00 108.00 36.00 1111 1 56-Pin SSOP 179.99 108.00 108.00 36.00 * Entries 00111 & 01111 are 250MHz on the B & C revision. * Internal Pull-Up Resistor 087505/24/04 ** Internal Pull-Down Resistor ICS954119 954119 Datasheet Pin Description PIN PIN PIN NAME DESCRIPTION TYPE 1 GND PWR Ground pin. 2 PCICLK3 OUT PCI clock output. 3 PCICLK4 OUT PCI clock output. 4 PCICLK5 OUT PCI clock output. 5 GND PWR Ground pin. 6 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 7 PCICLK F0 OUT Free running PCI clock not affected by PCI STOP . 3.3V tolerant input for CPU frequency selection. Refer to input electrical 8 FSLA/PCICLK F1 I/O characteristics for Vil FS and Vih FS values. / 3.3V PCI free running clock output. 3.3V tolerant input for CPU frequency selection. Refer to input electrical 9 FSLB/PCICLK F2 I/O characteristics for Vil FS and Vih FS values./ 3.3V PCI free running clock output. 10 VDD48 PWR Power pin for the 48MHz output.3.3V Latched select input for 24/48MHz output / 24/48MHz clock output. 11 **SEL24 48 /24 48MHz I/O 1=24MHz, 0 = 48MHz. 12 USB 48MHz OUT 48.00MHz USB clock 13 GND PWR Ground pin. 14 DOTT 96MHz OUT True clock of differential pair for 96.00MHz DOT clock. 15 DOTC 96MHz OUT Complement clock of differential pair for 96.00MHz DOT clock. Vtt PwrGd is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin 16 Vtt PwrGd /PD IN used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 17 PCIEXT0 OUT True clock of differential PCI Express pair. 18 PCIEXC0 OUT Complement clock of differential PCI Express pair. 19 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V 20 GND PWR Ground pin. 21 PCIEXT1 OUT True clock of differential PCI Express pair. 22 PCIEXC1 OUT Complement clock of differential PCI Express pair. 23 PCIEXT2 OUT True clock of differential PCI Express pair. 24 PCIEXC2 OUT Complement clock of differential PCI Express pair. 25 GND PWR Ground pin. True clock of differential pair for S-ATA support. 26 SRCCLKT OUT +/- 300ppm accuracy required. Complement clock of differential pair for S-ATA support. 27 SRCCLKC OUT +/- 300ppm accuracy required. 28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 087505/24/04 2