954141 Datasheet Programmable Timing Control Hub for Next Gen P4 processor Recommended Application: Features/Benefits: CK410 compliant clock Programmable output frequencies Programmable output skew. Output Features: Programmable spread percentage for EMI control. 2 - 0.7V current-mode differential CPU pairs Programmable watch dog safe frequency. 6 - 0.7V current-mode differential SRC pair Supports tight ppm accuracy clocks for Serial-ATA 1 - 0.7V current-mode differential CPU ITP/SRC Supports spread spectrum modulation, 0 to -0.5% selectable pair down spread, 0.25% center spread, and 0.3% 6 - PCI (33MHz) center spread 3 - PCICLK F, (33MHz) free-running Uses external 14.318MHz crystal, external crystal load 1 - USB, 48MHz caps are required for frequency tuning 1 - DOT, 96MHz, 0.7V current differential pair Supports undriven differential CPU, SRC pair in PD 1 - REF, 14.318MHz for power management. Key Specifications: CPU/SRC outputs cycle-cycle jitter < 85ps PCI outputs cycle-cycle jitter < 250ps +/- 300ppm frequency accuracy on CPU & SRC clocks Functionality Pin Configuration Bit2 Bit1 Bit0 CPU SRC SATA PCI Bit4 Bit3 VDDPCI156 PCICLK2 FSLC FSLB FSLA MHz MHz MHz MHz GND255 PCICLK1 0 000 0 266.66 100.00 100.00 33.33 PCICLK3354 PCICLK0 0 000 1 133.33 100.00 100.00 33.33 453 PCICLK4 FS C L 0 001 0 200.00 100.00 100.00 33.33 PCICLK5552 REFOUT 0 001 1 166.66 100.00 100.00 33.33 GND651 GND 0 0 1 0 0 333.33 100.00 100.00 33.33 VDDPCI750 X1 100.00 100.00 100.00 33.33 0 010 1 849 ITP EN/PCICLK F0 X2 0 011 0 400.00 100.00 100.00 33.33 PCICLK F1948 VDDREF 200.00 100.00 100.00 33.33 0 011 1 PCICLK F2 10 47 SDATA 266.66 133.33 133.33 33.33 0 100 0 VDD48 11 46 SCLK 133.33 133.33 133.33 33.33 0 100 1 USB 48MHz 12 45 GND 200.00 133.33 133.33 33.33 0 101 0 GND 13 44 CPUCLKT0 166.66 125.00 125.00 33.33 14 43 0 101 1 DOTT 96MHz CPUCLKC0 333.33 125.00 125.00 33.33 DOTC 96MHz 15 42 VDDCPU 0 110 0 16 41 FS B CPUCLKT1 100.00 133.33 133.33 33.33 L 0 110 1 Vtt PwrGd /PD 17 40 CPUCLKC1 400.00 133.33 133.33 33.33 0 111 0 FS A 18 39 IREF L 0 111 1 200.00 133.33 133.33 33.33 SRCCLKT1 19 38 GNDA 1 0 0 0 0 269.33 101.00 101.00 33.67 20 37 SRCCLKC1 VDDA 1 000 1 134.66 101.00 101.00 33.67 VDDSRC 21 36 CPUCLKT2 ITP/SRCCLKT 7 1 001 0 202.00 101.00 101.00 33.67 SRCCLKT2 22 35 CPUCLKC2 ITP/SRCCLKC 7 1 001 1 168.33 101.00 101.00 33.67 SRCCLKC2 23 34 VDDSRC 1 010 0 274.66 103.00 103.00 34.33 SRCCLKT3 24 33 SRCCLKT6 1 010 1 137.33 103.00 103.00 34.33 SRCCLKC3 25 32 SRCCLKC6 1 011 0 206.00 103.00 103.00 34.33 SRCCLKT4 SATA 26 31 SRCCLKT5 1 011 1 171.66 103.00 103.00 34.33 SRCCLKC4 SATA 27 30 SRCCLKC5 1 100 0 279.99 105.00 105.00 35.00 VDDSRC 28 29 GND 1 100 1 140.00 105.00 105.00 35.00 56-Pin SSOP and TSSOP 1 101 0 210.00 105.00 105.00 35.00 * Internal Pull-Up Resistor 1 101 1 174.99 105.00 105.00 35.00 ** Internal Pull-Down Resistor 1 110 0 287.99 108.00 108.00 36.00 1 110 1 144.00 108.00 108.00 36.00 1 111 0 216.00 108.00 108.00 36.00 1 111 1 179.99 108.00 108.00 36.00 0934A03/30/09 ICS954141 954141 Datasheet Pin Description PIN PIN NAME TYPE DESCRIPTION 1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GND PWR Ground pin. 3 PCICLK3 OUT PCI clock output. 4 PCICLK4 OUT PCI clock output. 5 PCICLK5 OUT PCI clock output. 6 GND PWR Ground pin. 7 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI STOP . ITP EN: latched input to select pin functionality 8 ITP EN/PCICLK F0 I/O 1 = CPU ITP pair 0 = SRC pair 9 PCICLK F1 OUT Free running PCI clock not affected by PCI STOP . 10 PCICLK F2 OUT Free running PCI clock not affected by PCI STOP . 11 VDD48 PWR Power pin for the 48MHz output.3.3V 12 USB 48MHz OUT 48.00MHz USB clock 13 GND PWR Ground pin. 14 DOTT 96MHz OUT True clock of differential pair for 96.00MHz DOT clock. 15 DOTC 96MHz OUT Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical 16 FSLB IN characteristics for Vil FS and Vih FS values. Vtt PwrGd is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used 17 Vtt PwrGd /PD IN to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 3.3V tolerant input for CPU frequency selection. Refer to input electrical 18 FSLA IN characteristics for Vil FS and Vih FS values. 19 SRCCLKT1 OUT True clock of differential SRC clock pair. 20 SRCCLKC1 OUT Complement clock of differential SRC clock pair. 21 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 22 SRCCLKT2 OUT True clock of differential SRC clock pair. 23 SRCCLKC2 OUT Complement clock of differential SRC clock pair. 24 SRCCLKT3 OUT True clock of differential SRC clock pair. 25 SRCCLKC3 OUT Complement clock of differential SRC clock pair. 26 SRCCLKT4 SATA OUT True clock of differential SRC/SATA pair. 27 SRCCLKC4 SATA OUT Complement clock of differential SRC/SATA pair. 28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 0934A03/30/09 2