954204 Datasheet Programmable Timing Control Hub for Mobile P4 Systems Recommended Application: PCI outputs cycle-cycle jitter < 500ps CK410M Compliant Main Clock with Integrated LCD Spread +/- 300ppm frequency accuracy on CPU & SRC clocks Spectrum Clock. +/- 100ppm frequency accuracy on USB clocks Features/Benefits: Output Features: Supports tight ppm accuracy clocks for Serial-ATA and 2 - 0.7V current-mode differential CPU pairs SRC 5 - 0.7V current-mode differential SRC pair for SATA and Supports programmable spread percentage and PCI-E frequency 1 - 0.7V current-mode differential CPU/SRC selectable Uses external 14.318MHz crystal, external crystal load pair caps are required for frequency tuning 4 - PCI (33MHz) Supports undriven differential CPU, SRC pair in PD 2 - PCICLK F, (33MHz) free-running for power management. 1 - USB, 48MHz CLKREQ pins to support SRC power management. 1 - DOT, 96MHz, 0.7V current differential pair 1 - REF, 14.318MHz 1 - 0.7V current-mode differential LCD/SRC selectable pair. Key Specifications: CPU outputs cycle-cycle jitter < 85ps SRC outputs cycle-cycle jitter < 125ps Pin Configuration Functionality CPU SRC PCI REF USB DOT VDDPCI156 PCICLK2 FS C FS B FS A GND255 PCI/SRC STOP MHz MHz MHz MHz MHz MHz PCICLK3354 CPU STOP 0 0 0 266.67 100.00 33.33 14.318 48.00 96.00 PCICLK4453 FS C/TEST SEL L 0 0 1 133.33 100.00 33.33 14.318 48.00 96.00 PCICLK5552 REFOUT 0 1 0 200.00 100.00 33.33 14.318 48.00 96.00 GND651 GND 0 1 1 166.67 100.00 33.33 14.318 48.00 96.00 VDDPCI750 X1 1 0 0 333.33 100.00 33.33 14.318 48.00 96.00 ITP EN/PCICLK F0849 X2 1 0 1 100.00 100.00 33.33 14.318 48.00 96.00 *SELSRC LCDCLK /PCICLK F1948 VDDREF 1 1 0 400.00 100.00 33.33 14.318 48.00 96.00 Vtt PwrGd /PD 10 47 SDATA 1 1 1 200.00 100.00 33.33 14.318 48.00 96.00 VDD48 11 46 SCLK FS A/USB 48MHz 12 45 GND L FS C is a three-level input. Please see V and V specifications in the 1. GND 13 44 CPUCLKT0 IL FS IH FS DOTT 96MHz 14 43 CPUCLKC0 Input/Supply/Common Output Parameters Table for correct values. Also refer DOTC 96MHz 15 42 VDDCPU to the Test Clarification Table. FS B/TEST MODE 16 41 CPUCLKT1 L FS B and FS A are low-threshold inputs. Please see the V and V 2. IL FS IH FS LCDCLK SST/SRCCLKT0 17 40 CPUCLKC1 specifications in the Input/Supply/Common Output Parameters Table for LCDCLK SSC/SRCCLKC0 18 39 IREF correct values. SRCCLKT1 19 38 GNDA SRCCLKC1 20 37 VDDA VDDSRC 21 36 CPUCLKT2 ITP/SRCCLKT7 SRCCLKT2 22 35 CPUCLKC2 ITP/SRCCLKC7 SRCCLKC2 23 34 VDDSRC SRCCLKT3 24 33 CLKREQA * SRCCLKC3 25 32 CLKREQB * SRCCLKT5 SRCCLKT4 SATA 26 31 SRCCLKC4 SATA 27 30 SRCCLKC5 VDDSRC 28 29 GND 56-pin TSSOP *100Kohm Pull-Up Resistor 0933E11/21/17 ICS954204 954204 Datasheet Pin Description PIN PIN NAME PIN TYPE DESCRIPTION 1 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 2 GND PWR Ground pin. 3 PCICLK3 OUT PCI clock output. 4 PCICLK4 OUT PCI clock output. 5 PCICLK5 OUT PCI clock output. 6 GND PWR Ground pin. 7 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI STOP . ITP EN: latched input to select pin functionality 8 ITP EN/PCICLK F0 I/O 1 = CPU ITP pair 0 = SRC pair Latched input select for LCD ss/ SRCCLK output frequency: 9 *SELSRC LCDCLK /PCICLK F1 I/O 0 = LCD, 1 = SRCCLK/ 3.3V free-running PCI clock output. Vtt PwrGd is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used 10 Vtt PwrGd /PD IN to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 11 VDD48 PWR Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical 12 FSLA/USB 48MHz I/O characteristics for Vil FS and Vih FS values. / Fixed 48MHz USB clock output. 3.3V. 13 GND PWR Ground pin. 14 DOTT 96MHz OUT True clock of differential pair for 96.00MHz DOT clock. 15 DOTC 96MHz OUT Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil FS and Vih FS values. TEST MODE is a real time 16 FSLB/TEST MODE IN input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. True clock of LCDCLK SS output / True clock of SRCCLK differential pair. 17 LCDCLK SST/SRCCLKT0 OUT Selected by SEL LCDCLK Complementary clock of LCDCLK SS output / Complementary clock of 18 LCDCLK SSC/SRCCLKC0 OUT SRCCLK differential pair. Selected by SEL LCDCLK 19 SRCCLKT1 OUT True clock of differential SRC clock pair. 20 SRCCLKC1 OUT Complement clock of differential SRC clock pair. 21 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 22 SRCCLKT2 OUT True clock of differential SRC clock pair. 23 SRCCLKC2 OUT Complement clock of differential SRC clock pair. 24 SRCCLKT3 OUT True clock of differential SRC clock pair. 25 SRCCLKC3 OUT Complement clock of differential SRC clock pair. 26 SRCCLKT4 SATA OUT True clock of differential SRC/SATA pair. 27 SRCCLKC4 SATA OUT Complement clock of differential SRC/SATA pair. 28 VDDSRC PWR Supply for SRC clocks, 3.3V nominal 0933E11/21/17 2