Programmable Timing Control Hub for 954206B Mobile P4 Systems DATASHEET General Description Features/Benefits The 954206B is a CK410M Compliant clock synthesizer. Supports tight ppm accuracy clocks for Serial-ATA and 954206B provides a single-chip solution for mobile systems PCI Express built with Intel P4-M processors and Intel mobile chipsets. Supports programmable spread percentage and frequency 954206B is driven with a 14.318MHz crystal and generates Uses external 14.318MHz crystal, external crystal load CPU outputs up to 400MHz. It provides the tight ppm accuracy caps are required for frequency tuning required by Serial ATA and PCI Express. Supports undriven differential CPU, PCI Express pair in PD for power management. Recommended Application PEREQ pins to support PCI Express and SATA power CK410M Compliant Main Clock management. Output Features Key Specifications 2 - 0.7V current-mode differential CPU pairs CPU outputs cycle-cycle jitter < 85ps 4 - 0.7V current-mode differential PCI Express*pairs PCI Express outputs cycle-cycle jitter < 125ps 1 - 0.7V current-mode differential CPU/PCI Express SATA outputs cycle-cycle jitter < 125ps selectable pair PCI outputs cycle-cycle jitter < 500ps 1 - 0.7V current-mode differential SATA pair 300ppm frequency accuracy on CPU, PCI Express and 1 - 0.7V current-mode differential LCDCLK/PCI Express SATA clocks selectable pair 100ppm frequency accuracy on USB clocks 1 - 0.7V current-mode differential PCI Express/Clock Request pair Pin Assignment 4 - PCI (33MHz) VDDPCI 1 56 PCICLK2/REQ SEL** 2 - PCICLK F, (33MHz) free-running GND 2 55 PCI/SRC STOP PCICLK3 3 54 CPU STOP 1 - USB, 48MHz PCICLK4 4 53 REF1/FS C/TEST SEL L 1 - DOT, 96MHz, 0.7V current differential pair PCICLK5 5 52 REF0 GND 6 51 GND 2 - REF, 14.318MHz VDDPCI 7 50 X1 ITP EN/PCICLK F0 8 49 X2 *SELPCIEX LCDCLK /PCICLK F1 9 48 VDDREF Vtt PwrGd /PD 10 47 SDATA VDD4811 46SCLK FS A/USB 48MHz 12 45 GND L GND 13 44 CPUCLKT0 DOTT 96MHz 14 43 CPUCLKC0 DOTC 96MHz 15 42 VDDCPU FS B/TEST MODE 16 41 CPUCLKT1 L LCDCLK SS/PCIEX0T 17 40 CPUCLKC1 LCDCLK SS/PCIEX0C 18 39 IREF PCIEXT1 19 38 GNDA PCIEXC1 20 37 VDDA VDDPCIEX 21 36 CPUCLKT2 ITP/PCIEXT6 PCIEXT2 22 35 CPUCLKC2 ITP/PCIEXC6 PCIEXC2 23 34 VDDPCIEX PCIEXT3 24 33 PEREQ1 */PCIEXT5 PCIEXC3 25 32 PEREQ2 */PCIEXC5 SATACLKT 26 31 PCIEXT4 SATACLKC 27 30 PCIEXC4 VDDPCIEX 28 29 GND 56-pin TSSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor 954206B FEBRUARY 22, 2016 1 2016 Integrated Device Technology, Inc. 954206B954206B DATASHEET Functional Block Diagram Table 1: Frequency Selection Table CPU PCIEX PCI REF USB DOT FS C B6b2 FS B B6b1 FS A B6b0 L L L MHz MHz MHz MHz MHz MHz Spread % 0 0 0 266.66 100.00 33.33 14.318 48.00 96.00 0.5% Down 0 0 1 133.33 100.00 33.33 14.318 48.00 96.00 0.5% Down 0 1 0 200.00 100.00 33.33 14.318 48.00 96.00 0.5% Down 0 1 1 166.66 100.00 33.33 14.318 48.00 96.00 0.5% Down 1 0 0 333.33 100.00 33.33 14.318 48.00 96.00 0.5% Down 1 0 1 100.00 100.00 33.33 14.318 48.00 96.00 0.5% Down 1 1 0 400.00 100.00 33.33 14.318 48.00 96.00 0.5% Down 1 1 1 200.00 100.00 33.33 14.318 48.00 96.00 0.5% Down PROGRAMMABLE TIMING CONTROL HUB FOR MOBILE P4 SYSTEMS 2 FEBRUARY 22, 2016